Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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18 resultados
Resultados da Pesquisa
- Saturation threshold voltage degradation in deep-submicrometer fully depleted SOI nMOSFETs operating in cryogenic environments(2005-10-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
- Analog operation of uniaxially strained FD SOI nMOSFETs in cryogenic temperatures(2007-10-04) Michelly De Souza; Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
- Influence of temperature on the operation of strained triple-gate FinFETs(2008-10-09) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.
- Thermal sensing performance of lateral SOI PIN diodes in the 90 - 400 K range(2009-10-08) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio Pavanello
- Effect of substrate rotation on the analog performance of triple-gate FinFETs(2009-10-08) Marcelo Antonio Pavanello; MARTINO, J. A.; SOMOEN, E.; COLLAERT, N.; CLAEYS, C.
- Fin shape influence on the analog performance of standard and strained MuGFETs(2010-10-14) BÜHLER, Rudolf Theoderich; MARTINO, J. A; AGOPIAN, P. G. D.; Renato Giacomini; SIMOEN, E.; CLAEYS, C.
- Comparison between the behavior of submicron Graded-Channel SOI nMOSFETs with fully- and partially-depleted operations in a wide temperature range(201-10-14) Michelly De Souza; EMAM, M.; VANHOENACKER-JANVIER, D.; RASKIN, J. P.; FLANDRE, D.; Marcelo Antonio Pavanello
- Electrical characterization of SOI solar cells in a wide temperature range(2010-10-14) Michelly De Souza; BULTEEL, O.; FLANDRE, D.; Marcelo Antonio Pavanello
- Analog operation of junctionless transistors at cryogenic temperatures(2010-10-14) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C. W.; FERAIN, I.; DEHDASHTI AKHAVAN, N.; YAN, R.; RAZAVI, P.; YU, R.; KRANTI, A.; COLINGE, J. P.
- Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors(2011-10-11) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this work an asymmetric self-cascode (SC) structure implemented in a 150nm technology have been studied as a function of the threshold voltage and length of both transistors in the structure, aiming to improve the analog characteristics of FD SOI transistors. Experimal results indicate that this structure provided improvement in comparison to single and symmetric (SC) transistors, and that it depends on the saturation voltage of both transistors. The effect of threshold voltage and length variation of both transistors have been analyzed through 2D numerical simulations. The obtained results showed that the analog characteristics of the A-SC is improved both by reducing V T,2 and increasing L 1 and/or L 2, although there would be a maximum M 2 length in which no significant g D reduction is observed. By properly choosing these parameters, a g D reduction of more than one order of magnitude can be achieved. The A-SC has shown to provide an intrinsic voltage gain improvement of more than 20dB in comparison to single devices with similar effective channel length. © 2011 IEEE.