Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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13 resultados
Resultados da Pesquisa
- Analog parameters of strained non-rectangular triple gate FinFETs(2010-01-05) BÜHLER, Rudolf Theoderich; Renato Giacomini; MARTINO, J. A.The strained silicon technology together to the reduction of the temperature is studied in this paper on trapezoidal triple gate FinFETs, through three-dimensional numerical simulation, with particular focus on analog parameters. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes demonstrated that, although the strained silicon technology provided higher intrinsic voltage gain, the fin shape can have a major role in analog parameters, helping to improve those parameters under certain circumstances. Higher intrinsic voltage gains were obtained for strained devices with top fin width larger than bottom. ©The Electrochemical Society.
- Sidewall angle influence on the FinFET analog parameters(2007-09-06) Renato Giacomini; MARTINO, J. A.; Marcelo Antonio PavanelloThe width variations along the vertical direction, due to process limitations, that appear in some fabricated FinFETs lead to non-rectangular cross-sectional shapes. One of the most frequent shapes is the trapezoidal (inclined sidewalls). These geometry variations may cause some changes in the device electrical characteristics. This work analyses the influence of the sidewall inclination angle on analog parameters, such as voltage gain, transconductance, output conductance, threshold voltage and also on the corner effects, through 3-D numeric simulation. © The Electrochemical Society.
- Simple analytical model to study the ZTC bias point in FinFETs(2007-05-11) BELLODI, M.; CAMILLO, L. M.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work we present a simple analytical model to study the Zero Temperature Coefficient (ZTC) bias point in FinFETs operating from room temperature up to 573 K. Three-dimensional simulations are carried out and compared with experimental results to qualify the results. © The Electrochemical Society.
- Non-vertical sidewall angle influence on triple-gate FinFETs corner effects(2007-05-11) Renato Giacomini; MARTINO J. A.Some fabricated FinFET devices present width variations along the vertical direction due to fabrication process limitations. These variations lead to non-rectangular cross-section shapes. One of the most frequent shapes is the trapezoidal (plane and inclined sidewalls). Another identified phenomenon in multiple-gate devices such as FinFETs is the corner effect, which occurs due to the overlapping of the influences of two gate planes near the device corners. This paper addresses the variation of the corner effect as a function of the sidewall inclination angle, through 3-D numeric simulation. A set of devices of several inclination angles and body doping levels were simulated. The corner effect depends on the inclination angle, specially for higher doping levels. © The Electrochemical Society.
- Low temperature operation of undoped body triple-gate FinFETs from an analog perspective(2007-09-06) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS R.; COLLAERT, N.; CLAEYS, CThis paper studies the temperature reduction influence on some analog figures of merit of n-type triple-gate FinFETs with undoped body, using DC measurements. It is demonstrated that the temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L=90 nm FinFET is degraded by 3 dB when the temperature reduces from 300 K down to 100 K. A comparison with planar single gate fully depleted SOI reveals that the temperature degradation of the output conductance in FinFETs is less temperature-dependent. © The Electrochemical Society.
- Temperature influences on FinFETs with undoped body(2007-05-11) Marcelo Antonio Pavanello; MARTINO J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.This work presents a study, based on DC measurements, of the temperature influence on the performance of nMOS triple-gate FinFETs with high-κdielectrics, TiN gate material and an undoped body. FinFETs show smaller threshold voltage variations with temperature than planar fully-depleted SOI MOSFETs. The subthreshold slope reduced with the temperature and approached the ideal value at lower temperatures In the temperature range under study the mobility increases linearly as the temperature is reduced and the dominating mobility degradation factor is phonon scattering. The DIBL has been evaluated and no temperature dependence has been found. Finally, the series resistance has been also extracted and demonstrates a reduction as the temperature is reduced due to the mobility improvement. © The Electrochemical Society.
- Fin width influence on the harmonic distortion of standard and strained FinFETs operating in saturation(2009-09-03) Rodrigo Doria; CERDEIRA. A.; MARTINO J. A; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloThis work compares the harmonic distortion of standard and biaxially strained FinFETs aiming at analog applications such as amplifiers. The harmonic distortion has been extracted for devices operating as single transistor amplifiers. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated for devices with several fin widths. For a fairer analysis, the influence of the open-loop voltage gain (Av) in devices with different dimensions has also been considered generating the figures of merit THD/Av and HD3/Av. According to the analysis, narrower devices have overcome the wider ones and conventional FinFETs have shown to be more attractive than the strained ones for analog purposes. Narrower standard FinFETs exhibited up to 20 dB THD/Av better in relation to the strained ones. © The Electrochemical Society.
- Influence of fin width and channel length on the performance of buffers implemented with standard and strained triple-gate nFinFETs(2009-09-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion. © The Electrochemical Society.
- Harmonic distortion analysis of SOI triple gate FinFETs applied to 2-MOS balanced structures(2009-05-29) Rodrigo Doria; MARTINO, J. A.; CERDEIRA, A.; Marcelo Antonio PavanelloThis work presents an evaluation of the non-linearities exhibited in 2-MOS resistive structures composed by triple gate FinFETs with several fin widths down to 30 nm. The harmonic distortion has been analysed in terms of its third order component (HD3) as a function of the gate voltage, the input amplitude voltage and the fin width. The linearity has also been analysed with respect to the on-resistance, which constitutes a key parameter in such circuits. Along the harmonic distortion evaluation, the non-linearity causes are pointed out. At lower gate voltages, wider devices present smaller HD3 with respect to the narrower ones, while the contrary occurs at higher gate voltages. ©The Electrochemical Society.
- Three-dimensional simulation of biaxially strained triple-gate FinFETs: A method to compute the fin width and channel length dependences on device electrical characteristics(2010-01-05) Rodrigo Doria; Marcelo Antonio PavanelloStrained devices have been the focus of recent research works due to the boost in the carrier mobility providing a drain current enhancement. Consequently, simulating strained transistors become of major importance in order to predict their characteristics. However, the non-uniformity of the stress distribution creates a dependence of the strain on the device dimensions. This dependence cannot be easily considered in a TCAD simulation. This work shows that the definition of an analytical function for the strain components can overcome this drawback in the stress simulation. Maximum transconductance gain was used as the key parameter to compare simulated and experimental data. The results obtained show mat the simulations with the analytical function agree wim the measurements. ©The Electrochemical Society.