Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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12 resultados
Resultados da Pesquisa
Artigo de evento 0 Citação(ões) na Scopus Charge-based continuous explicit equations for the transconductance and output conductance of submicron graded-channel SOI mosfet's(2006-09-01) Michelly De Souza; Marcelo Antonio PavanelloThis paper presents charge-based continuous explicit equations for the transconductance and output conductance of submicron Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. Short-channel effects like channel length modulation, velocity saturation and drain-induced barrier lowering have been considered in the proposed expressions. Experimental results were used to test the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement as well as smooth transitions between the different regions of operation, validating the proposed equations. © 2006 The Electrochemical Society.- Sidewall angle influence on the FinFET analog parameters(2007-09-06) Renato Giacomini; MARTINO, J. A.; Marcelo Antonio PavanelloThe width variations along the vertical direction, due to process limitations, that appear in some fabricated FinFETs lead to non-rectangular cross-sectional shapes. One of the most frequent shapes is the trapezoidal (inclined sidewalls). These geometry variations may cause some changes in the device electrical characteristics. This work analyses the influence of the sidewall inclination angle on analog parameters, such as voltage gain, transconductance, output conductance, threshold voltage and also on the corner effects, through 3-D numeric simulation. © The Electrochemical Society.
- Low temperature operation of undoped body triple-gate FinFETs from an analog perspective(2007-09-06) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS R.; COLLAERT, N.; CLAEYS, CThis paper studies the temperature reduction influence on some analog figures of merit of n-type triple-gate FinFETs with undoped body, using DC measurements. It is demonstrated that the temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L=90 nm FinFET is degraded by 3 dB when the temperature reduces from 300 K down to 100 K. A comparison with planar single gate fully depleted SOI reveals that the temperature degradation of the output conductance in FinFETs is less temperature-dependent. © The Electrochemical Society.
- Influence of fin width and channel length on the performance of buffers implemented with standard and strained triple-gate nFinFETs(2009-09-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion. © The Electrochemical Society.
- Global and/or local strain influence on p- and nMuGFET analog performance(2011-01-05) AGOPIAN, P. G. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work, the analog performance is evaluated for tri-gate p-and nMuGFETs processed with and without the implementation of different global or local strain engineering techniques. For n-channel devices, the intrinsic voltage gain showed to be worse for strained devices when the fin is narrow. Only for wider fins the voltage gain increases with the strain efficiency due to mobility enhancement. Besides the voltage gain, the transconductance, output conductance and Early Voltage are also evaluated. In spite of the smaller impact of strain engineering, pMuGFETs show better analog behavior for all studied parameters. ©The Electrochemical Society.
- The roles of the electric field and the density of carriers in the improved output conductance of junctionless nanowire transistors(2011-01-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C. W.; FERAIN, I.; DEHDASHTI AKHAVAN, N.; YAN, R.; RAZAVI, P.; YU, R.; KRANTI, A.; COLINGE, J. P.This paper evaluates the roles of the electric field (E) and the density of carries (n) in the drain conductance of Junctionless Nanowire Transistors (JNTs). The behavior of E and n presented by JNTs with the variation of the gate and the drain voltages has been compared to the one presented by Inversion Mode (M) Trigate devices of similar dimensions. It has been shown that the lower drain output conductance exhibited by Junctionless transistors with respect to the IM ones is correlated not only to the differences in the mobility and its degradation but also to the electric field, the density of carries and the first order derivative of these variables with respect the drain voltage. ©The Electrochemical Society.
- Comparison between SOI nMOSFET's under uniaxial and biaxial mechanical stress in analog applications(2011-09-02) DE SOUZA, M. A. S.; SOUZA, F. N.; Michelly De Souza; Marcelo Antonio PavanelloThis work presents a study comparing the analog performance of uniaxially and biaxially strained planar Silicon-on-Insulator nMOSFETs for a wide range of channel lengths. The study is performed via two-dimensional numerical and process simulation and supported by experimental measurements. The comparison between devices from the same technology with these two strained techniques demonstrated that higher intrinsic voltage gain is obtained for biaxial mechanical stress. However, the transconductance is higher for uniaxial mechanical stress for shorter devices (below 550 nm) leading to larger unity gain frequency. On the other hand, despite both strain techniques degrades the output conductance, this degradation with channel length shortening is less pronounced for devices under biaxial mechanical stress. © The Electrochemical Society.
- Liquid helium temperature operation of graded-channel SOI nMOSFETs(2012-09-02) Michelly De Souza; KILCHYTSHA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThis work reports, for the first time, the operation of Graded-Channel SOI nMOSFETs at liquid helium temperature. As expected, for all measured devices it has been observed that at 4.2K the transconductance increases with respect to room temperature as a consequence of the mobility rise. On the opposite hand, all the studied devices demonstrated a degradation of the output conductance with temperature reduction. However, this degradation is attenuated below 90K. As a consequence, an increase of the Early voltage and of the intrinsic voltage gain were obtained, in contrast to the data reported in the literature, for devices operating down to 100K. It is demonstrated that GC SOI presented larger Early voltage increase at 4.2K than at room temperature. The rise of the voltage gain promoted by GC architecture has shown to be constant with temperature down to 4.2K. © The Electrochemical Society.
- Analysis of the self-heating effect in UTBOX devices(2012-08-30) RODRIGUES, M.; CRUZ, E. O.; Milene Galeti; MARTINO, J. A.This work presents a study of the self-heating effect (SHE) on -n type UTBOX devices. Thinner buried oxide indicated a reduction on degradation caused by the SH phenomenon as shown by drain current and transient time. Addressed to that, a smaller output conductance variation with the frequency was also related where a higher frequency is required for the SHE emergence. The ground plane region was also considered on the UTBOX devices indicating to be favorable in suppress the SHE. © The Electrochemical Society.
- Influence of 45° Substrate Rotation on the Analog Performance of Biaxially Strained-Silicon SOI MuGFETs(2013-05-16) DE SOUZA, M. A. S.; Rodrido Doria; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloIn this work the influence of the substrate rotation on the analog performance of strained SOI MuGFETs is presented. Measurements performed in fabricated devices show a degradation of the maximum transconductance at both linear and saturation regime. The substrate rotation has no influence on the output conductance. The intrinsic voltage gain and the unit gain frequency were extracted and presented a reduction promoted by substrate rotation, being more evident for a narrow fin. © The Electrochemical Society.