Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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8 resultados
Resultados da Pesquisa
- Analysis of the scattering mechanisms in the accumulation layer of junctionless nanowire transistors at high temperature(2019-08-05) RIBEIRO, T. A.; Marcelo Antonio Pavanello© 2019 IEEE.This work studies the effects of high temperature on the scattering mechanisms of Junctionless Nanowire Transistors with several fin width from nanowire to quasi-planar devices. With the variation of the temperature it was possible to analyze the impact of the scattering mechanisms on the devices. For nanowire devices at room temperature a degradation of up to 19% was seen from the maximum mobility to the mobility at higher gate bias to around 15% at 500K, while quasi-planar devices show a degradation of around 12% for all temperatures. Further analysis shows that the impact of the surface roughness for nanowires increase the degradation of these devices, where a reduction of its degradation at higher temperature shows the phonon scattering as the main scattering mechanism.
- Multi-layers lateral SOI PIN photodiodes for solar cells applications(2019-08-05) SILVA, F. A. DA; Rodrigo Doria; ANDRADE, M. G. C. DE© 2019 IEEE.In this paper, a lateral PIN photodiode based on a SOI wafer has been studied through numerical simulations. This device can be used as a solar cell embedded in a CMOS circuit in order to propose autonomous ultralow-power circuits (ULP). Efficiency behavior has been analyzed for different semiconductor materials and configurations in order to reach the best performance. The results indicate that a layer with a different semiconductor, with different characteristics such as forbidden band, mobility and light absorption, improves the generated power in the device, suggesting that the cell can feed circuits that need larger power.
- Harmonic distortion in symmetric and asymmetric self-cascodes of UTBB FD SOI planar MOSFETs(2019-08-05) D'OLIVEIRA, L. M.; KILCHYTSKA, V.; FLANDRE, D.; Michelly De Souza© 2019 IEEE.This paper presents an analysis of the harmonic distortion extracted from simulated results of symmetric and asymmetric self-cascode devices (S-SC and A-SC, respectively) composed by ultra-thin body and BOX fully depleted silicon-on-insulator planar MOSFETs 28 nm technological node. The results show that the A-SC effectively increases the operating drain current range for lower distortion. Comparisons with the literature show that the A-SC structures are a promising option for enhancing the circuit design flexibility for advanced MOSFETs.
- Impact of substrate bias on the mobility of n-type-gate SOI nanowire MOSFETs(2019-08-05) BERGAMASHI, F. E.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; PAZ, B. C.; Marcelo Antonio PavanelloThis work presents the impact of substrate bias on the mobility of high-κ gate n-type Ω-gate SOI nanowire MOS transistors. The analysis is performed through experimental measurements and tridimensional numerical simulations. Mobility and its degradation coefficients are extracted using the Y-function method. The results showed that back bias increase has a beneficial effect on mobility for negative voltages and up to 10V, due to reduction in surface roughness scattering. But for higher back bias levels, mobility starts undergoing severe degradation. Simulations show that strong positive back bias drags the inversion layer down to the second interface, where mobility is shown to be lower.
- Analysis of the substrate effect by the capacitive coupling in SOI UTBB Transistors(2019-08-30) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2019 IEEE.The goal of this work is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with the application of a selected set of back gate biases (VSUB) through DC and AC simulations. A set of different ground planes (GP) arrangements has been considered. It has been shown that the degradation due to the substrate effects increases as the substrate bias is reduced. According to the analysis, it could be observed the GP type influences the capacitive coupling of the structure as the back gate bias is varied. Additionally, it has been shown that the presence of the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the device.
- Boosting the performance of MOSFET operating under a huge range of high temperature by using the octagonal layout style(2019-08-30) GALEMBECK, E. H. S.; SWART, J.; SILVA, G. A.; Salvador Gimenez© 2019 IEEE.This paper performs an experimental comparative study of a huge variation of temperature influence (from 300K to 573K) in planar Metal-Oxide-Semiconductor (MOS) Field-Effect-Transistors (MOSFETs), which are implemented with the octagonal (Octo MOSFETs, OM) and rectangular (Rectangular MOSFETs, RM) layout styles, regarding the same bias conditions. The devices were manufactured regarding a Complementary MOS (CMOS) Integrated Circuits (ICs) manufacturing process of 180 nm. The main results have shown that the OM is capable of keeping active the Longitudinal Corner Effect (LCE) and PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), which are intrinsic present in its structure, resulting a higher electrical performing in the relation to their RM counterparts, such as the OM saturation drain current (IDS_SAT) and transconductance (gm) are approximately three and two times, respectively, better as compared to those found in its RM counterpart. Therefore, the octagonal layout style for MOSFETs can be considered an alternative layout strategy to boost the electrical performance of the MOSFETs, without causing any additional burden to the CMOS ICs manufacturing process.
- Applicability of charge pumping technique for evaluating the effect of interface traps in junctionless nanowire transistors(2019-08-30) FONTE, E. T.; TREVISOLI, R.; Rodrido Doria© 2019 IEEE.A study of Junctionless Nanowire Transistors (JNTs) is presented in this work, with emphasis on verifying the applicability of the charge pumping method for the analysis of interface traps. To the best of our knowledge, this is the first work to use this method in JNTs. The first step is the analysis of the performance using numerical simulations. It is stated that a transient current is observed in the devices with the charge pumping method application and increases with the trap density. Simulated and experimental data of Junctionless Nanowire Transistors show how this method can be useful and its applicability to verify the JNTs interface quality.
- Boosting the ionizing radiation tolerance in the mosfets matching by using diamond layout style(2019-08-30) PERUZZI, V. V.; CRUZ, W. S. D.; SILVA, G. A. D.; TEIXEIRA, R. C.; SEIXAS JUNIOR, L. E.; Salvador Gimenez© 2019 IEEE.There are a lot of initiatives to improve the devices matching (dog bone layout, common centroid layout, dummy devices, etc.). Another layout technique, not yet used by integrated circuits (ICs) companies, is the utilization of non-conventional layout styles (hexagonal, octagonal, ellipsoidal, etc.) for MOSFETs, thanks to the Longitudinal Corner Effect (LCE), Parallel Connection of MOSFETs with different channel Lengths Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in Bird's Beaks Regions (DEMPAMBBRE). In this context, this paper describes an experimental comparative study of the devices matching of Metal-Oxide-Semiconductor Field Effect Transistors (130 nm Silicon-Germanium Bulk), n-type (nMOSFETs) implemented with Diamond (hexagonal) and standard rectangular layout styles, regarding a sample of 189 transistors which were exposure to different X-rays ionizing radiations. Considering some relevant electrical parameters considered in this work, the results indicate that the Diamond layout style with α angle equal to 90° is capable of boosting by at least 40% the device matching in relation to one observed with standard (rectangular) MOSFET counterparts in irradiation environment, considering they present the same gate areas, channel widths and bias conditions. Therefore, the Diamond layout style can be considered another hardness-by-design (HBD) layout strategy to boost the electrical performance and ionizing radiation tolerance of MOSFETs.