Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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77 resultados
Resultados da Pesquisa
- Junctionless nanowire transistors effective channel length extraction through capacitance characteristics(2023-10-05) SILVA, E. M.; TREVISOLI, R.; Rodrigo Doria© 2023 Elsevier LtdThis work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
- Analysis of the scattering mechanisms in the accumulation layer of junctionless nanowire transistors at high temperature(2019-08-05) RIBEIRO, T. A.; Marcelo Antonio Pavanello© 2019 IEEE.This work studies the effects of high temperature on the scattering mechanisms of Junctionless Nanowire Transistors with several fin width from nanowire to quasi-planar devices. With the variation of the temperature it was possible to analyze the impact of the scattering mechanisms on the devices. For nanowire devices at room temperature a degradation of up to 19% was seen from the maximum mobility to the mobility at higher gate bias to around 15% at 500K, while quasi-planar devices show a degradation of around 12% for all temperatures. Further analysis shows that the impact of the surface roughness for nanowires increase the degradation of these devices, where a reduction of its degradation at higher temperature shows the phonon scattering as the main scattering mechanism.
- Modeling Quantum Confinement in Multi-Gate Transistors with Effective Potential(2022) SOARES, C. S.; BAIKADI, P. K. R.; ROSSETO, A. C. J.; Marcelo Antonio Pavanello; VASILESKA, D.; WIRTH, G. I.© 2022 IEEE.Particle-based Monte Carlo device simulators are an efficient tool to investigate the performance and reliability of transistors. The semiclassical theoretical model employed in the Monte Carlo device simulator is unsuccessful to describe some aspects of the multi-gate transistors that come from the quantum behavior of charge carriers. To take into consideration the space-quantization effects in these simulators, a quantum correction is necessary. We propose to include an effective potential in the Monte Carlo device simulator to address the wave-like behavior of electrons in n-type silicon FinFET and n-type silicon nanowire transistors. The effective potential has a unique parameter, which can be adjusted to find a line density using an Effective Potential-Poisson solver that matches with the line density calculated using a Schrodinger-Poisson solver. We demonstrated that using the effective potential model, the effect of the electron confinement is well described.
- Junctionless Nanowire Transistor for Analog Applications: Cascode Current Mirror Configuration(2022-08-05) SHIBUTANI, A. B.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.In this paper, a cascode current mirror compounded by junctionless nanowire transistors is analyzed for the first time. Thus, the performance and the mirroring precision of the configuration were investigated considering the internal circuit feedback and the high output resistance. On this basis, symmetrical and asymmetrical configurations were examined to comprehend the junctionless nanowire transistor behavior as a current source.
- An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires(2022) Michelly De Souza; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.
- Analysis of Variability in Transconductance and Mobility of Nanowire Transistors(2022-08-22) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2022 IEEE.This work presents a comparison between the variability in junctionless nanowire transistors and inversion-mode nanowire transistors, looking at the transconductance, low-field mobility, linear and quadratic mobility degradation coefficients. To extract these parameters, the Y-Function method has been used. The obtained results shows differences in mobility and transconductance matching coefficients, indicating that mobility influence is not the only source of transconductance variation.
- Variability Modeling in Triple-Gate Junctionless Nanowire Transistors(2022-01-05) TREVISOLI, R.; Marcelo Antonio Pavanello; Rodrigo Doria; CAPOVILLA, C.E.; BARRAUD, S.; Michelly De SouzaIEEEThis work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.
- NBTI Dependence on Temperature in Junctionless Nanowire Transistors(2021-07-27) GRAZIANO, N.; TREVISOLI, R.; Rodrigo, Doria©2021 IEEE.This paper discusses the nature of degradation by NBTI effect in pMOS junctionless devices when varying the temperature. The results were obtained through simulations validated to experimental data. Devices with different dimensions and doping, have been subjected to a temperature range that varies between 270 and 380 K. The simulations were performed for different values of VGT and as a result it is possible to observe that when increasing temperature up to 340 K, the threshold voltage variation due to NBTI is also increased. However, for larger temperatures the NBTI effect seems to stabilize or even reduce.
- Interface traps density extraction through transient measurements in junctionless transistors(2022-08-05) TEICEIRA DA FONTE, E.; TREVISOLI, R.; BARRAUD S.; Rodrigo Doria© 2022 Elsevier LtdThis paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.