Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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25 resultados
Resultados da Pesquisa
- Analog parameters of strained non-rectangular triple gate FinFETs(2010-01-05) BÜHLER, Rudolf Theoderich; Renato Giacomini; MARTINO, J. A.The strained silicon technology together to the reduction of the temperature is studied in this paper on trapezoidal triple gate FinFETs, through three-dimensional numerical simulation, with particular focus on analog parameters. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes demonstrated that, although the strained silicon technology provided higher intrinsic voltage gain, the fin shape can have a major role in analog parameters, helping to improve those parameters under certain circumstances. Higher intrinsic voltage gains were obtained for strained devices with top fin width larger than bottom. ©The Electrochemical Society.
- Impact of halo implantation on the lifetime assessment in partially depleted soi transistors(2006-11-03) Milene Galeti; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.This paper investigates the impact of the presence of a HALO implanted region on the lifetime analysis, based on a study of drain current switch-off transients. The latter were experimentally determined and compared with two-dimensional numerical simulations for PD SOI nMOSFET devices fabricated in a 0.13 μm CMOS technology. This study investigated for different channel lengths the drain current transient in relation with devices parameters such as the body potential, threshold voltage and the current density in the source/drain junctions. In the HALO devices the hole current density through the junctions between source/drain and body were not very significant, so that the influence of the junction is only due to the capacitive coupling between source/body and drain/body channel. For the channel length range studied (from 10 to 0.2μm), the transient time of HALO devices suffers from a 56% reduction. However, in the no HALO devices, there is beyond the capacitive coupling also a significant increase in the hole current density, causing a transient time reduction of 74%, for the same channel length range. copyright The Electrochemical Society.
- Sidewall angle influence on the FinFET analog parameters(2007-09-06) Renato Giacomini; MARTINO, J. A.; Marcelo Antonio PavanelloThe width variations along the vertical direction, due to process limitations, that appear in some fabricated FinFETs lead to non-rectangular cross-sectional shapes. One of the most frequent shapes is the trapezoidal (inclined sidewalls). These geometry variations may cause some changes in the device electrical characteristics. This work analyses the influence of the sidewall inclination angle on analog parameters, such as voltage gain, transconductance, output conductance, threshold voltage and also on the corner effects, through 3-D numeric simulation. © The Electrochemical Society.
- Physical characterization and reliability aspects of MuGFETs(2007-09-06) CLAEYS, C.; SIMOEN, E.; RAFI, J. M.; Marcelo Antonio Pavanello; MARTINO, J. A.Multi-gate devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling to the 32 nm and below technology nodes. Worldwide much attention is given to FinFET and MuGFET device architectures. This paper reviews some physical characterization and reliability aspects of such devices. Attention is given to aspects such as transient floating body effects, their performance at both high and low temperatures, gate coupling effects and their low frequency noise behavior. In addition, their potential radiation hardness in view of space applications is outlined. © The Electrochemical Society.
- Influence of the N-type FinFET width on the zero temperature coefficient(2007-09-07) BELLODI, M.; MARTINO, J. A.; CAMILO, L. M.; SIMOEN, E.; CLAEYS, C.This paper presents the influence of the Fin width dimension on the Zero Temperature Coefficient (ZTC) behavior for devices operating at high temperatures (from room temperature up to 573K). Besides this, a simple analytical model is presented in order to describe the ZTC behavior as the temperature increases. Three-dimensional simulations are carried out and compared with experimental results to support the interpretation presented along this work. © The Electrochemical Society.
- Simple analytical model to study the ZTC bias point in FinFETs(2007-05-11) BELLODI, M.; CAMILLO, L. M.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work we present a simple analytical model to study the Zero Temperature Coefficient (ZTC) bias point in FinFETs operating from room temperature up to 573 K. Three-dimensional simulations are carried out and compared with experimental results to qualify the results. © The Electrochemical Society.
- Low temperature operation of undoped body triple-gate FinFETs from an analog perspective(2007-09-06) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS R.; COLLAERT, N.; CLAEYS, CThis paper studies the temperature reduction influence on some analog figures of merit of n-type triple-gate FinFETs with undoped body, using DC measurements. It is demonstrated that the temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L=90 nm FinFET is degraded by 3 dB when the temperature reduces from 300 K down to 100 K. A comparison with planar single gate fully depleted SOI reveals that the temperature degradation of the output conductance in FinFETs is less temperature-dependent. © The Electrochemical Society.
- Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs(2008-09-04) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.This work studies the influence of the fin width on the intrinsic voltage gain of standard and strained Si (sSOI) n-type triple-gate FinFETs with high-k dielectrics and metal gate. It is demonstrated that independent of the fin width the application of strain improves the device transconductance. On the other hand, the device output conductance shows a high dependence on the fin width in strained FinFETs with respect to standard ones. The output conductance degrades if narrow fins are used and improves for wide fins. Narrow strained FinFETs show a degradation of the Early voltage compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. © The Electrochemical Society.
- Influence of fin width and channel length on the performance of buffers implemented with standard and strained triple-gate nFinFETs(2009-09-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion. © The Electrochemical Society.
- Harmonic distortion analysis of SOI triple gate FinFETs applied to 2-MOS balanced structures(2009-05-29) Rodrigo Doria; MARTINO, J. A.; CERDEIRA, A.; Marcelo Antonio PavanelloThis work presents an evaluation of the non-linearities exhibited in 2-MOS resistive structures composed by triple gate FinFETs with several fin widths down to 30 nm. The harmonic distortion has been analysed in terms of its third order component (HD3) as a function of the gate voltage, the input amplitude voltage and the fin width. The linearity has also been analysed with respect to the on-resistance, which constitutes a key parameter in such circuits. Along the harmonic distortion evaluation, the non-linearity causes are pointed out. At lower gate voltages, wider devices present smaller HD3 with respect to the narrower ones, while the contrary occurs at higher gate voltages. ©The Electrochemical Society.
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