Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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6 resultados
Resultados da Pesquisa
- Sidewall angle influence on the FinFET analog parameters(2007-09-06) Renato Giacomini; MARTINO, J. A.; Marcelo Antonio PavanelloThe width variations along the vertical direction, due to process limitations, that appear in some fabricated FinFETs lead to non-rectangular cross-sectional shapes. One of the most frequent shapes is the trapezoidal (inclined sidewalls). These geometry variations may cause some changes in the device electrical characteristics. This work analyses the influence of the sidewall inclination angle on analog parameters, such as voltage gain, transconductance, output conductance, threshold voltage and also on the corner effects, through 3-D numeric simulation. © The Electrochemical Society.
- Physical characterization and reliability aspects of MuGFETs(2007-09-06) CLAEYS, C.; SIMOEN, E.; RAFI, J. M.; Marcelo Antonio Pavanello; MARTINO, J. A.Multi-gate devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling to the 32 nm and below technology nodes. Worldwide much attention is given to FinFET and MuGFET device architectures. This paper reviews some physical characterization and reliability aspects of such devices. Attention is given to aspects such as transient floating body effects, their performance at both high and low temperatures, gate coupling effects and their low frequency noise behavior. In addition, their potential radiation hardness in view of space applications is outlined. © The Electrochemical Society.
- Analysis of matching in graded-channel SOI MOSFETs(2007-09-06) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents an analysis of mismatch in Graded-Channel (GC) SOI MOSFETs. Experimental results show that GC devices present poorer threshold voltage and drain current matching in comparison to conventional SOI counterpart. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to predict the matching behavior both in linear and saturation regions. © The Electrochemical Society.
- Application of double gate graded-channel SOI in MOSFET-C balanced structures(2007-05-11) Rodrigo Doria; Marcelo Antonio Pavanello; CERDEIRA, A.; RASKIN J. P.; FLANDRE, D.This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices when applied in 2-MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive. © The Electrochemical Society.
- Low temperature operation of undoped body triple-gate FinFETs from an analog perspective(2007-09-06) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS R.; COLLAERT, N.; CLAEYS, CThis paper studies the temperature reduction influence on some analog figures of merit of n-type triple-gate FinFETs with undoped body, using DC measurements. It is demonstrated that the temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L=90 nm FinFET is degraded by 3 dB when the temperature reduces from 300 K down to 100 K. A comparison with planar single gate fully depleted SOI reveals that the temperature degradation of the output conductance in FinFETs is less temperature-dependent. © The Electrochemical Society.
- Temperature influences on FinFETs with undoped body(2007-05-11) Marcelo Antonio Pavanello; MARTINO J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.This work presents a study, based on DC measurements, of the temperature influence on the performance of nMOS triple-gate FinFETs with high-κdielectrics, TiN gate material and an undoped body. FinFETs show smaller threshold voltage variations with temperature than planar fully-depleted SOI MOSFETs. The subthreshold slope reduced with the temperature and approached the ideal value at lower temperatures In the temperature range under study the mobility increases linearly as the temperature is reduced and the dominating mobility degradation factor is phonon scattering. The DIBL has been evaluated and no temperature dependence has been found. Finally, the series resistance has been also extracted and demonstrates a reduction as the temperature is reduced due to the mobility improvement. © The Electrochemical Society.