Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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10 resultados
Resultados da Pesquisa
- Asymmetric self-cascode current-voltage constructing algorithm for analog figures-of-merit extraction(2018-08-31) D' OLIVEIRA, L. M.; Michelly De Souza; KILCHYTSKA, V.; FLANDRE. D.© 2018 IEEE.This paper proposes an analysis of a self-cascode IV constructing algorithm for the extraction of DC analog figures of merit, namely the transconductance, output conductance and intrinsic voltage gain. The algorithm was applied on input tables of measured single Fully-depleted Silicon on Insulator (FDSOI) nMOSFETs and was validated on the measured self-cascode association of these devices. The results show an appropriate accuracy, that reflect trends and values with low error.
- Experimental lateral PIN gated photodiode RGB discrimination with multiple incident optical power(2018-08-31) BÜHLER, Rudolf Theoderich; MONTESANI, G. J.; Renato Giacomini© 2018 IEEE.The lateral PIN gated photodiode is used here as a RGB color and incident optical power discriminator through experimental measurements. The ability to discriminate the color and the incident optical power through conventional MOS fabrication process without the need of optical filters and concentrate in a single device is evaluated through experimental data on lateralPIN gated photodiode to demonstrate the viability of using it to discriminate both color and optical power. Numerical simulations are also used to analyze the use of mechanical strain to boostits performance and the changes that it causes in the generated photocurrent.
- Back bias impact on effective mobility of p-type nanowire SOI MOSFETs(2018-08-27) PAZ, B .C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloIn this work we investigated the impact of back bias on the effective mobility of p-type Ω-gate nanowire SOI MOSFETs. Evaluation is performed through both measurements and 3D numerical simulations. Electrostatic potential, electric field and holes density are studied through simulations to explain transconductance degradation with back bias increase. Holes mobility linear dependence on back bias is found to be related to the inversion channel density and its position along the silicon thickness. Besides, this work also sheds light on the dependence of the drain current in vertically stacked NW with back bias, as its behavior is determined by the bottom Ω-gate level.
- Low-frequency noise investigation in long-channel fully depleted inversion mode n-type SOI nanowire(2018-08-27) MOLTO, A. R.; PAZ, B. C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis work presents a Low-Frequency Noise (LFN) investigation in fully depleted n-type Silicon-On-Insulator (SOI) nanowire transistors working in linear region with VDS = 50mV. Long-channel devices of 1μ {m and 10μ {m are evaluated. A wide range of fin width is considered in the LFN analysis, from 15nm up to 105nm. The results showed a flicker noise (1/FF) behavior and a decrease of normalized noise SID/IDs2 with gate voltage overdrive increase for frequencies bellow 500Hz. Above this frequency, it was possible to see that generation and recombination noise with 1/f2 decay overlaps the flicker noise, becoming the predominant noise source. The cut-off frequency increases with gate voltage overdrive while the gamma exponent decreases. Gamma reduces from 1.3 to 0.9 and from 0.95 to 0.65 for devices with channel length of 1 μ {m and 10μ {m, respectively. A major noise variation of about one order of magnitude with gate voltage overdrive increase was observed in devices of 1 μ {m long in comparison to channel length of 10μ {m. The devices showed weak noise dependence on fin width due to mobility decrease as nanowires become narrower.
- Numerical simulation and analysis of transistor channel length and doping mismatching in GC SOI nMOSFETs analog figures of merit(2018-08-31) ALVES, C. R.; Michelly De Souza; FLANDRE, D.© 2018 IEEE.This paper presents a two-dimensional numerical simulation study of mismatching on the analog characteristics of fully-depleted graded-channel (GC) SOI MOSFET. The study aims at identifying the mismatching sources that affect the analog performance of GC SOI transistors. The simulations were performed imposing length and doping concentration variations and analyzing its impact on important electrical parameters such as threshold voltage and subthreshold slope, as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.
- Analysis of the output conductance degradation with the substrate bias in SOI UTB and UTBB transistors(2018-08-31) FERNO COSTA, J.; TREVISOLI, R.; Rodrigo Doria© 2018 IEEE.The goal of this work is to present the behavior of the output conductance in Ultra-Thin Body (UTB) and Ultra-Thin Body and Buried Oxide (UTBB) SOI {MOSFETs with the application of a selected set of back gate biases (VSUB) through AC simulations, in devices with and without considering the effect of the ground plane. It has been shown that the output conductance degradation due to self-heating and substrate effects increases as the substrate bias is reduced. The output conductance degradation by self-heating presents a reduction of about 52% and by substrate effects of 57% by simply increasing the back bias from-2V up to 2 V.
- Using statistical student's t-test to qualify the electrical performance of the diamond MOSFETs(2018-08-31) PERUZZI, V. V.; DA SILVA, G. A; RENAUX, C.; FLANDRE, D; Salvador Gimenez© 2018 IEEE.This study describes the use of the Student's t-Test to qualify statistically the impact of using the Diamond (hexagonal) layout style in the electrical performance of Silicon-On-Insulator (SOI) MOSFETs. A sample of 360 SOI Metal-Oxide-{Semiconductor Field Effect Transistors, n-type (nMOSFETs) were used to perform this experimental work. Regarding the SOI MOSFETs saturation drain current (IDSsat), the results of this study indicate that the Diamond SOI nMOSFETs for all considered angles present higher IDSsat mean values in comparison to those measured from the standard rectangular SOI MOSFET counterparts, considering that they present the same gate areas, channel width and bias conditions (with a bias condition of 1V between the drain and source and a bias condition of 0.4V between the gate and source). For all the other α angle, that is, 36.9 °, 53.1 °, 90.0 °, 126.9 ° and 143.1 °, the DSnM IDSsat((W/L) mean value is higher than the CSnM IDSsat((W/L) mean value in an order of 51.3%, 37.6%, 40.9%, 19.0% and 10.6%, respectively. Therefore, this statistical approach can be used as a power statistical tool to validate electrical parameters and figures of merit of devices and integrated circuits regarding the nanoelectronics area.
- Experimental analysis of self-heating effects using the pulsed IV method in junctionless nanowire transistors(2018-08-27) BERGAMASHI, F. E.; MARINIELLO, G.; BARRAUD, S.; Marcelo Antonio PavanelloThis paper discusses the occurrence of self-heating in Junctionless Nanowire Transistors, observed through drain current degradation in the transient regime. The analysis is made by performing experimental measurements using the Pulsed IV method in transistors with varied dimensions. It is shown that the junctionless nanowire's susceptibility to self-heating is not high enough to significantly affect the transistor's characteristics, where for all cases current degradation lower than 4.5% is seen.
- Impact of the octagonal layout style for MOSFETs using 180nm Bulk CMOS ICs technology node(2018-Aug-31) LOESCH, D. S.; Salvador Gimenez; SWART, J. W.; Marcilei Aparecida GuazzelliThis paper aims to evaluate the impact of the octagonal layout style for MOSFETs regarding the 180nm Bulk CMOS ICs technology node. The main results of this study show that the nMOSFETs with octagonal gate geometries are capable of improving the drain current, Early voltage, intrinsic voltage gain, and on-state drain to source resistance about 150%, 800%, 66% and 50%, respectively, in relation to the standard rectangular MOSFET counterparts, regarding the same bias conditions. Therefore, the LCE and PAMDLE effects continue being actives regarding this 180 nm Bulk CMOS ICs technology node.
- Influence of the intrinsic length on the behavior of PIN diodes fabricated on SOI substrates working as solar cells(2018-10-26) SILVA, F.; Rodrigo Doria; Michelly De Souza© 2018 IEEE.This work evaluates the influence of the intrinsic region length on the behavior of PIN diodes fabricated in the substrate of SOI wafers, operating as solar cells. The analysis has been performed in terms of efficiency and fill factor, fundamental parameters for the solar cell characterization. The studied cell has shown efficiency of about 7% to 8% and fill factor with average about 80%. Originally, ungated PIN devices have been considered in TCAD simulations. In the sequence, a gate has been placed over the intrinsic region of simulated devices and different biases (0V and 5V) were applied to compare the results with the ungated ones. Lastly, different operation temperatures have been applied into simulations, aiming to achieve results closer to real operation conditions.