Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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33 resultados
Resultados da Pesquisa
- Junctionless nanowire transistors effective channel length extraction through capacitance characteristics(2023-10-05) SILVA, E. M.; TREVISOLI, R.; Rodrigo Doria© 2023 Elsevier LtdThis work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.
- Extraction of the Back Channel Mobility in SOI Nanowire MOS Transistors under Substrate Biasing(2022-07-04) BERGAMASHI, F. E.; WIRTH, G. I.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an analysis of the effective mobility of SOI nanowire MOS transistors is performed by separating the mobility of electrons in the back channel, which is created when substrate bias is applied. Measurements are done in n-type devices with an Ω-gate structure and variable channel length. Both longer and shorter channel devices present higher mobility in the back channel, but strong mobility reduction is observed with the increase of the substrate bias, reaching values close to that of the front channel at strong back bias levels. This effect is independent of the applied gate voltage overdrive. Three-dimensional TCAD simulation validates the method used to separate the back channel mobility, showing that the front channel mobility is not changed by the increase in substrate bias.
- SOI UTBB Capacitive Cross-Coupling Effects in Ultimate Technological Nodes(2022-03-01) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to carry out an analysis of the effects of cross-coupling in a system composed of SOI UTBB MOSFETs in ultimate integration nodes through numerical simulations, validated with experimental data from literature. In this analysis, it could be observed that two devices located on the channel length direction provoke a reduced cross-coupling on each other. For devices located at distances below 50 nm, a capacitive parasitic coupling between the devices can be observed along with the thermal coupling effect.
- New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs(2022-01-05) GALEMBECK, E. H. S.; Salvador GimenezIEEEIt is known that the hexagonal (Diamond) layout style is capable of boosting the electrical performance and ionizing radiation tolerances of metal-oxide-semiconductor field-effect-transistors (MOSFETs). In order to further improve the figures of merit of these devices, it was proposed a hybrid gate geometry that is an evolution of the hexagonal layout style, entitled Half-Diamond. This innovative layout style is able to generate the same electrical effects that the Diamond is able to generate, and it is innovative because it is capable of further reducing the effective channel lengths of MOSFETs implemented with Diamond and rectangular layout styles. Thus, this work describes a comparative study by 3-D numerical simulations data and experimental data between the MOSFETs implemented with the Half-Diamond and Conventional layout styles. The main results found have indicated that the saturation drain current and transconductance of MOSFET layouted with Half-Diamond are 36% and 27% higher, respectively, than those measured in the Conventional MOSFET. Other results have shown that the innovative half-diamond layout style (HDLS) for MOSFETs is capable of reducing the dissipated electrical power in approximately 62% and, therefore, it is an alternative hardness-by-design strategy to remarkably improve complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) energy efficiency. Besides, the electrical behaviors of longitudinal corner effect (LCE), parallel connection of MOSFETs with different channel lengths effect (PAMDLE), and deactivation of parasitic MOSFETs in the bird's beak regions effect (DEPAMBBRE) of the MOSFETs implemented with the HDLS are studied in detail to justify the results found.
- Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors(2021-09-06) Michelly De Souza; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOR, O.; Marcelo Antonio PavanelloIn this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire n MOS transistors is presented. Die-to-die variability of threshold voltage and drain current is presented and compared to inversion mode nanowire with the same dimensions. Although the junctionless nanowires have shown larger threshold voltage matching coefficients than inversion mode devices, the variability obtained experimentally has shown to be smaller than predicted by some simulations reported in the literature. Also, it has been shown that as the channel length of junctionless nanowire transistors is reduced, the current variability becomes smaller than in inversion mode nanowires, at the same current level and dimensions.
- Influence of fin width and channel length on the performance of buffers implemented with standard and strained triple-gate nFinFETs(2009-09-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion. © The Electrochemical Society.
- 3D simulation of Triple-Gate MOSFETs(2010-05-19) CONDE, J.; CERDEIRA, A.; Marcelo Antonio Pavanello; KILCHYTSKA, V.; FLANDRE, D.In this paper we present a new approach of analyzing 3D structure for Triple-Gate MOSFETs with three different mesh regions, one at the top and two in the sidewalls of the fin, which allows the consideration of different carrier mobility at each region due to the crystalline orientation and technological processing. A procedure for the extraction of the mobility parameters in each region is developed. Validation of the proposed structure was made for a FinFET arrays with fixed channel length and different fin widths, obtaining a very good coincidence between experimental and simulated characteristics. © 2010 IEEE.
- Three-dimensional simulation of biaxially strained triple-gate FinFETs: A method to compute the fin width and channel length dependences on device electrical characteristics(2010-01-05) Rodrigo Doria; Marcelo Antonio PavanelloStrained devices have been the focus of recent research works due to the boost in the carrier mobility providing a drain current enhancement. Consequently, simulating strained transistors become of major importance in order to predict their characteristics. However, the non-uniformity of the stress distribution creates a dependence of the strain on the device dimensions. This dependence cannot be easily considered in a TCAD simulation. This work shows that the definition of an analytical function for the strain components can overcome this drawback in the stress simulation. Maximum transconductance gain was used as the key parameter to compare simulated and experimental data. The results obtained show mat the simulations with the analytical function agree wim the measurements. ©The Electrochemical Society.
- X-ray radiation effects in the circular-gate transistors(2011-01-05) CIRNE, K. H.; Marcilei Aparecida Guazzelli; DE LIMA, J. A.; SEIXAS JUNIOR, L. E.; Salvador GimenezThis work performs two experimental comparative analyses of the x-ray radiation effects in the Conventional, Wave and Overlapping-Circular-Gate nMOSFETs. In the first experiment, the x-ray radiation influence is studied without biasing the devices during the irradiation process, considering two channel lengths and after they have been exposed up to a x-ray irradiation of 1.5 Grad and with a dose ratio of 22 Mrad/min. The second one performs an experimental comparative study of the x-ray radiation influence between the Conventional and Overlapping-Circular Gate nMOSFET for a channel length equal to 12 μm, when they are submitted to the x-ray irradiation of 60 Mrad and maintaining the same bias conditions (overdrive gate and drain voltages) during the irradiation process. In both studies, we observe that the Overlapping-Circular Gate layout style presents higher x-ray irradiation robustness than those found in the other transistors studied, due to the absence of the bird's beak in Overlapping-Circular Gate MOSFET. ©The Electrochemical Society.
- An analytical model for the non-linearity of triple gate SOI MOSFETs(2011-01-05) Rodrigo Doria; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloThis work proposes a physically-based analytical model for the non-linearity of Triple-Gate MOSFETs. The model describes the second order harmonic distortion (HD2), usually the major non-linearity source, as a function of the device dimensions, the series resistance, the low field mobility and the mobility degradation factor (θ). The model was applied to transistors of different channel lengths and fin widths and allowed to conclude that θ is the parameter which most contributes for the increase of HD2. The model was validated for both unstrained and strained FinFETs. ©The Electrochemical Society.