Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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Resultados da Pesquisa
- Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs(2006-01-05) SIMOEN, E.; CLAEYS. C.; LUKYANCHIKOVA, N.; GARBER, N.; SMOLANKA, A.; DER AGOPIAN, P. G.; MARTINO, J. A.The impact of using a twin-gate (TG) configuration on the Electron Valence-Band (EVB) tunnelling-related floating-body effects has been studied in partially depleted (PD) SOI MOSFETs belonging to a 0.13 μm CMOS technology. In particular, the influence on the so-called linear kink effects (LKEs), including the second peak in the linear transconductance (gm) and the associated Lorentzian noise overshoot was investigated. It is shown that while there is a modest reduction of the second gm peak, the noise overshoot may be reduced by a factor of 2. At the same time, little asymmetry is observed when switching the role of the slave and the master transistor, in contrast to the case of the impact ionization related kink effects. Two-dimensional numerical simulations support the observations and show that both the gm, the second gm peak and the body potential are changed in the TG structure compared with a single transistor. © 2005 Elsevier Ltd. All rights reserved.
- Reliability performance characterization of SOI FinFets(2009-06-02) CLAEYS, C.; PUT, S.; RAFI, J. M.; Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.FinFET devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling CMOS to 22 nm and below. Some physical characterization and reliability aspects of these devices are reviewed. Attention is given to transient floating body effects and low frequency noise, which may yield information on the materials' characteristics like carrier recombination lifetime or interface and oxide trap density. These methods can be useful to study the performance of these components under harsh operation conditions of low or high temperature, or at high bias voltages. ©2009 IEEE.
- Low-frequency noise in asymmetric self-cascode FD SOI nMOSFETs(2016-08-29) ASSALTI, R.; Rodrigo Doria; Marcelo Antonio Pavanello; Michelly De Souza; FLANDRE, D.This paper investigates the origin of low-frequency noise in Asymmetric Self-Cascode Fully Depleted SOI nMOSFETs biased in linear regime with regards to the variation of gate voltage and the channel doping concentration through experimental results.
- Low-frequency noise investigation in long-channel fully depleted inversion mode n-type SOI nanowire(2018-08-27) MOLTO, A. R.; PAZ, B. C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis work presents a Low-Frequency Noise (LFN) investigation in fully depleted n-type Silicon-On-Insulator (SOI) nanowire transistors working in linear region with VDS = 50mV. Long-channel devices of 1μ {m and 10μ {m are evaluated. A wide range of fin width is considered in the LFN analysis, from 15nm up to 105nm. The results showed a flicker noise (1/FF) behavior and a decrease of normalized noise SID/IDs2 with gate voltage overdrive increase for frequencies bellow 500Hz. Above this frequency, it was possible to see that generation and recombination noise with 1/f2 decay overlaps the flicker noise, becoming the predominant noise source. The cut-off frequency increases with gate voltage overdrive while the gamma exponent decreases. Gamma reduces from 1.3 to 0.9 and from 0.95 to 0.65 for devices with channel length of 1 μ {m and 10μ {m, respectively. A major noise variation of about one order of magnitude with gate voltage overdrive increase was observed in devices of 1 μ {m long in comparison to channel length of 10μ {m. The devices showed weak noise dependence on fin width due to mobility decrease as nanowires become narrower.
- Back bias influence on low-frequency noise of n-type nanowires SOI MOSFETs(2019-02-11) MOLTO, A. R.; PAZ. B. C.; Rodrido Doria; Michelly De Souza; Marcelo Antonio Pavanello© 2018 IEEE.This work presents the influence of back (substrate) bias on the low-frequency noise of fully depleted inversion mode n-FET nanowire transistors with different fin widths. Several gate voltage overdrives were applied (from 0mV to 200mV) with devices working in linear regime. The results showed a noise increase for both positive and negative substrate biases (Vsub) and the changing of γ , from 0.9 with zero back bias down to 0.4 for Vsub = -40V. The results obtained for device with channel length of 1 μ m and fin width of 15nm show a decrease of the spectral noise density with the gate voltage overdrive increase for frequencies below 100Hz, which is characterized by mobility mechanism influence at the power spectrum density noise. It was also possible to see in these devices that the generation and recombination noise with decay of 1/f2 overlaps the 1/f γnoise for frequencies above 100Hz. It was also possible to see the noise increase with Wfin decrease as expected.
- Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors(2019) Trevisoli R.; Doria R.T.; Barraud S.; Pavanello M.A.© 2019 Elsevier B.V.The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the trap-related noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability.
- Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization(2017) Doria R.T.; Trevisoli R.; de Souza M.; Barraud S.; Vinet M.; Faynot O.; Pavanello M.A.© 2017 Elsevier B.V.This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. The study has been performed for devices with different channel lengths and doping concentrations biased close to the threshold and deep in linear regime. It has been shown that the surface potential of JNTs is strongly influenced by the substrate bias even above threshold. Thus, the drain current noise spectral density and the effective trap density can be improved or degraded depending on the bias applied to the substrate of the devices. Additionally, it is shown that, the variation on the substrate bias enables the evaluation of traps with different activation energy ranges, which is more evident in heavier doped devices due to the higher threshold voltage sensitivity to the substrate bias.
- Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45 rotated substrates(2013) Doria R.T.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.This paper studies the impact of the 45 substrate rotation on the low-frequency noise (LFN) of triple gate nFinFETs. The overall LFN has been extracted for both standard and 45 substrate rotated devices of several fin widths at different drain and gate voltage biases focusing on their operation in saturation regime. A general view of the mechanisms which govern the low-frequency noise in MOS devices is provided and a brief discussion on the physical origins of the LFN in the evaluated devices is carried out. It has been noted that the LFN in non-rotated (0 rotated) and 45 rotated devices operating in the linear regime shows 1/f behavior independent on the gate bias, whereas in the saturation regime both 1/f and Lorentzian (1/f2) noises are observed. The former one prevails at lower frequencies and the 1/f2 noise at higher ones. In this case, the corner frequency shows an exponential dependence on the gate bias. © 2013 Elsevier Ltd. All rights reserved.
- In-depth low frequency noise evaluation of substrate rotation and strain engineering in N-type triple gate SOI Finfets(2015) Doria R.T.; De Souza M.A.S.; Martino J.A.; Simoen E.; Claeys C.; Pavanello M.A.© 2015 Elsevier B.V. All rights reserved.This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained-rotated SOI n-type FinFETs, respectively, for several fin widths biased at different gate voltages. Additionally, the profile of the effective trap density is presented along the depth of the gate dielectric of the devices. It is shown that strained devices present higher noise than conventional ones, independent on the fin width, which can be explained by poorer interface quality observed in strained devices. On the other hand, the low frequency noise of narrow rotated devices, where the main conduction path changes from top to sidewalls, has shown to reduce as the interface integrity is improved by substrate rotation. All the evaluated devices presented 1/f noise as the dominant noise component up to 1 kHz.
- Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors(2014) Doria R.T.; Trevisoli R.; De Souza M.; Pavanello M.A.This work presents an evaluation of the Low-Frequency Noise (LFN) exhibited by short-channel Junctionless Nanowire Transistors (JNTs). Unlike in previous works in which only the noise of n-type transistors was evaluated, this paper exhibits an analysis of both the LFN and the effective trap density of n- and p-type JNTs. The low-frequency noise is analyzed in terms of the channel length as well as doping concentration and has shown to be nearly independent on the former parameter when the device is biased above threshold and to decrease with the raise of the latter. Also, carrier number fluctuations dominate the LFN in nMOS JNTs whereas an important mobility fluctuation component is present in the pMOS ones. The effective trap density of JNTs has shown to be in the order of 1019 cm-3 eV-1, presenting its maximum around 1.4 nm away from the silicon/gate dielectric interface independently on the device type or doping concentration. © 2014 Elsevier Ltd. All rights reserved.