Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
Navegar
60 resultados
Resultados da Pesquisa
Artigo de evento 1 Citação(ões) na Scopus Halo effects on 0.13 μm floating-body partially depleted SOI n-Mosfets in low temperature operation(2003-10-12) MARTINO, J. A.; Marcelo Antonio Pavanello; SIMOEN, E.; CLAEYS, C.This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation, Parameters such as the Drain Induced Barrier Lowering and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 - 300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature.Artigo de evento 1 Citação(ões) na Scopus Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures(2004-09-11) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.The use of partially depleted deep-submicrometer SOI nMOSFETs in mixed mode applications is discussed in terms of channel engineering and temperature of operation. It is shown that the halo implantation used to obtain better digital characteristics degrades the gain and the unity gain frequency in comparison to devices that are not subjected to this implantation.Artigo de evento 1 Citação(ões) na Scopus Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMoSFETs(2005-09-07) Milene Galeti; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.This paper presents an analysis of the gate oxide thickness and temperature influence on the carrier generation lifetime determination. The study is accomplished through two-dimensional numerical simulations in partially depleted SOI nMOSFETs and compared with experimental data of devices fabricated with a 0.13 μm SOI CMOS technology. The temperature varied from 20°C to 80°C and the gate oxide thickness between 1.5 nm and 3.5 nm. Beyond the generation lifetime, other electric parameters were also analyzed as the threshold voltage, the surface potential, the activation energy and the gate current. A reduction of surface potential was observed for an increase in the gate oxide thickness, specially in the steady state surface potential. In the present study, the decrease in gate oxide thickness caused a maximum of 2% variation in the activation energy. For the step bias used, the gate current is not enough large to control the body charging and makes it less sensitive to transient effects.Artigo de evento 2 Citação(ões) na Scopus Comparison between bulk and floating body partially depleted SOI nMOSFETS for high frequency analog applications operating from 300 K down to 95 K(2005-09-07) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.A comparison between deep-submicrometer bulk and floating-body partially depleted (PD) SOI nMOSFET operation for high frequency analog applications is performed from room temperature down to 95 K. The transistor intrinsic gain, cutoff frequency and bias current are used as figures of merit for this comparison. It is demonstrated that bulk transistors can have larger intrinsic gain at any temperature of operation due to their larger Early voltage. On the other hand, the cutoff frequency is improved in PD SOI without halo due to the larger carrier mobility and velocity saturation. Also PD SOI without halo reaches a frequency of 13 GHz at 95 K, whereas bulk and PD SOI with halo reach 11 GHz for the same load capacitance of 100 fF.Artigo de evento 1 Citação(ões) na Scopus Analysis of the linear kink effect in partially depleted SOI nMOSFET's(2005-09-07) AGOPIAN, P. G.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work, the occurrence of the linear kink effect (LKE) in PD SOI nMOSFETs is investigated experimentally and by two-dimensional simulations. The experimental dependence of the LKE on the drain voltage and the channel length is reported, showing a reduction of the second peak in the transconductance when the transistor channel length decrease. By two-dimensional numerical simulations, the impact of various parameters on this second peak has been studied, namely, the gate current level, the carrier lifetime, the increase of the body potential and the threshold voltage variation.Artigo de evento 1 Citação(ões) na Scopus The temperature mobility degradation influence on the ZTC of PD and FD SOI MOSFETs(2005-05-20) CAMILO, L. M.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.The Zero Temperature Coefficient (ZTC) is observed experimentally in partially and fully depleted SOI MOSFET fabricated in a 0.13μm SOI CMOS technology. A simple model to study the behavior of gate voltage at ZTC (V ZTC) is proposed. The influence of the temperature mobility degradation in VZTC: is analyzed for PD and FD devices. Experimental results show that the temperature mobility degradation is larger in FD than in PD devices which is responsible for the VZTC decrement observed in FD instead of the increment observed in PD when the temperature increase. A good agreement is found in spite of the simplification used for VZTC model as a function of temperature.Artigo de evento 2 Citação(ões) na Scopus Analysis of deep submicrometer bulk and fully depleted SOI nmosfet analog operation at cryogenic temperatures(2005-05-20) Marcelo Antonio Pavanello; Joao Antonio Martino; SIMOEN, E.; CLAEYS, C.The increased demand for mixed mode digital-analog circuits is playing an important role nowadays. As the temperature of operation is decreased well-known improvements in the digital characteristics as reduction of the subthreshold slope and increased carrier mobility are obtained leading to better performance characteristics without scaling the dimensions. In this work, the impact of the temperature reduction on the analog characteristics of deep submicrometer bulk and fully depleted SOI nMOSFETs is compared. It is shown that the Early voltage does not vary appreciably with temperature and the intrinsic gain is substantially improved in bulk deep submicrometer transistors. On the other hand, deep submicrometer fully depleted SOI can operate at reduced bias current to bias the same load in base-band applications.Artigo de evento 0 Citação(ões) na Scopus Series resistance influence on the linear kink effect in twin-gate partially depleted SOI nMOSFETs(2007-09-01) DER AGOPIAN, P. G.; Joao Antonio Martino; SIMOEN, E.; CLAEYS, C.This work elaborates on the influence of the series resistance on the linear kink effect (LKE) in twin-gate partially depleted (PD) Silicon-on-Insulator (SOI) nMOSFETs. The study is based on two-dimensional numerical simulations and is validated by experimental results. A relationship between the total resistance and the apparent mobility degradation factor is reported, showing that the twin-gate structure and a conventional SOI transistor with an external resistance both present a similar LKE reduction, The asymmetric behavior of the body potential with the interchange of the master and slave transistor of the twin-gate structure will be also shown. © 2006 The Electrochemical Society.Artigo 2 Citação(ões) na Scopus Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs(2010-09-05) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion.- Saturation threshold voltage degradation in deep-submicrometer fully depleted SOI nMOSFETs operating in cryogenic environments(2005-10-03) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.