Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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7 resultados
Resultados da Pesquisa
- High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs(2023-01-05) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Pavanello M. A.AuthorIn this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.
- Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures(2022-07-04) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K and 580 K. The study is conducted using experimental data, corroborated with 3D TCAD simulations. It is demonstrated that the GIDL current normalized by the total fin width is larger in nanosheet MOSFET than for the nanowire at high temperatures. Additionally, the nanosheet device presents a larger variation of the normalized GIDL current with the temperature than the nanowire one.
- Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures(2022-08-22) PRATES, R. R.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work aims to present the electrical properties of junctionless and inversion-mode nanowires MOSFETs in the temperature range from 300 K to 580 K. Devices with different fin widths are compared. The comparison is performed using experimental data looking for some of the fundamental electrical parameters of these transistors such as threshold voltage, inverse subthreshold slope, current, and carrier mobility over the temperature.
- Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs(2021-08-27) RODRIGUES, J. C.; MARINELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature. c2021 IEEE.
- Electrical characterization of stacked SOI nanowires at low temperatures(2022-05-05) RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis work presents the electrical characterization of 2-level vertically stacked nanowire MOSFETs with variable fin widths in the temperature range from 93 K to 400 K. The basic electrical properties, such as threshold voltage, subthreshold slope, and carrier mobility are examined in the linear region with low VDS. In sequence, certain analog figures of merit such as the transconductance, the output conductance, and the voltage gain are assessed in saturation. The threshold voltage variation with temperature is linear and slightly increases for wider devices, which was satisfactorily validated by an analytical model for 3D devices. Additionally, the subthreshold slope remains close to the theoretical limit in the whole range of temperatures. The intrinsic voltage gain is weakly temperature-sensitive in the studied range regardless of the fin width. On the other hand, it increases for narrow devices in all temperatures.
- New method for individual electrical characterization of stacked SOI nanowire MOSFETs(2017-10-18) PAZ, B.C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloA new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Q-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.
- Impact of substrate bias on the mobility of n-type-gate SOI nanowire MOSFETs(2019-08-05) BERGAMASHI, F. E.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; PAZ, B. C.; Marcelo Antonio PavanelloThis work presents the impact of substrate bias on the mobility of high-κ gate n-type Ω-gate SOI nanowire MOS transistors. The analysis is performed through experimental measurements and tridimensional numerical simulations. Mobility and its degradation coefficients are extracted using the Y-function method. The results showed that back bias increase has a beneficial effect on mobility for negative voltages and up to 10V, due to reduction in surface roughness scattering. But for higher back bias levels, mobility starts undergoing severe degradation. Simulations show that strong positive back bias drags the inversion layer down to the second interface, where mobility is shown to be lower.