Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
Navegar
23 resultados
Resultados da Pesquisa
- Charge Pumping-Based Method for Traps Density Extraction in Junctionless Transistors(2021) FONTE, E. T.; TREVISOLI, R.; Rodrido Doria© 2021 IEEE.A study of Junctionless Transistors (JNTs) is presented in this work, with emphasis on verifying the extraction of the interface traps density using the charge pumping method. To the best of our knowledge, this is the first work to use this method in JNTs. The method was applied to both simulated and experimental data and has shown satisfactory results.
- Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors(2012-01-05) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; DAS, S.; FERAIN, I.; Marcelo Antonio PavanelloThis paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model. © 2012 IEEE.
- Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements(2012-09-02) MARINIELLO, G.; Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire transistors have been recently proposed as an alternative to overcome the short channel effect caused by the reduction of the transistors dimensions. These devices behave like a gated resistor due to the lack of the p-n junctions in the channel/ source and channel/drain regions. The influence of doping concentration, silicon width, silicon height and gate oxide thickness on the intrinsic gate capacitances are presented in this paper by using three-dimensional numerical simulations and experimental results of fabricated devices. Also the influence of the applied drain bias in the components of the intrinsic gate capacitances is addressed. © The Electrochemical Society.
- Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance(2012-09-02) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (gD) with respect to single devices, resulting in an increase of VEA and AV, which can be higher than 30 dB depending on the bias conditions. © The Electrochemical Society.
- Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors(2012-09-02) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloJunctionless nanowire transistors have a constant doping profile from source to drain, providing a great scalability without the need of rigorously controlled doping gradients and activation techniques. Therefore, these devices are considered as promising for decananometer era. This work proposes an analytical model for the drain current in junctionless nanowire transistor (JNT) accounting for short channel effects and temperature dependence. Tridimensional numerical simulations of p-type devices have been performed to validate the model. Experimental data of n-type devices have also been used. © The Electrochemical Society.
- Drain current model for junctionless nanowire transistors(2012-03-17) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results. © 2012 IEEE.
- The role of the incomplete ionization on the operation of Junctionless Nanowire Transistors(2012-10-04) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; FERAIN, I.; DAS, S.; Pavanello M.A.The use of planar MOS devices for the sub-20 nm era has become a great challenge due to the loss of the gate control on the channel charges [1]. Multi-gate architecture provides a better electrostatic control, allowing a higher degree of miniaturization [1]. One of the major drawbacks of either planar or multi-gate extremely short devices is the formation of p-n junctions between source/drain and the channel, which requires precise thermal conditions in order to avoid the impurities diffusion into the channel. In this context, Junctionless Nanowire Transistors (JNTs) have been developed [2-3]. They consist of heavy doped silicon nanowires (N+ for nMOS and P+ for pMOS) surrounded by a gate stack. The device is doped from source to drain with the same element type and concentration, such that there are no gradients or junctions. Fig. 1 presents a schematic view (A) and the longitudinal section (B) of an nMOS JNT. These devices are based on bulk conduction [4] and have shown to provide better subthreshold slope, DIBL and analog properties than inversion-mode devices of similar dimensions [5-6]. Recent papers have shown the temperature (7) influence on the behavior of JNTs [7-8]. The main characteristic was the absence of the zero temperature coefficient (ZTC) bias, i.e. a point in which the drain current is almost the same independently of the temperature. In these papers, this absence has been attributed to the higher threshold voltage (Vm) and the lower mobility (μ) dependences on T [7]. This paper shows that JNTs can present a ZTC bias, which strongly depends on the series resistance. © 2012 IEEE.
- Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors(2012-10-04) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; FERAIN, I.; DAS, S.; Marcelo Antonio PavanelloMulti-gate architecture has been considered as one of the most viable alternatives to MOS devices scaling below 22 nm nodes [1] due to its stronger robustness to the short channel effects with respect to planar architectures. In short channel devices, the control of the gate over the channel charges dramatically decreases making the use of planar devices extremely challenging. Despite providing an improved coupling between gates and channel, conventional inversion mode (IM) multi-gate structures such as Trigate and FinFETs present p-n junctions between source/drain and channel, which can become an important bottleneck for ultimate technologies in which the formation of ultra-sharp junctions is needed in order to avoid the source/drain dopants diffusion into the channel. A novel multi-gate architecture so-called Junctionless Nanowire Transistor (JNT) was recently developed to overcome this bottleneck [2-3]. The JNT consists of a silicon nanowire surrounded by gate stack and is different from multi-gate IM devices due to its doping profile which is heavy and constant between source, channel and drain without any dopant gradients. The longitudinal sections of both a pMOS and an nMOS JNT are shown in Fig. 1 where the p-type is doped with boron and the n-type ones with phosphorous. The silicon nanowire needs to have a square-section small enough to be fully depleted at low gate voltages, turning off the device. Above threshold, the current flows mainly due to bulk conduction [4]. Several papers have shown the potentiality of the JNT for technological nodes beyond 10 nm [2-6] since it provides better DIBL, subthreshold slope and analog properties than IM multi-gate transistors of similar dimensions [5,6]. Although the Low-Frequency Noise (LFN) of JNTs has been treated in different papers [7,8], only long devices have been evaluated up to now and in none of them the LFN of pMOS was addressed as proposed in the current paper. © 2012 IEEE.
- Non-linear behavior of Junctionless nanowire transistors operating in the linear regime(2013-09-06) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; ESTRADA, M.; CERDEIRA, A.; Marcelo Antonio PavanelloThe linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature and the series resistance on the overall linearity have been evaluated. It is demonstrated that the increase of the series resistance improves the second order distortion and degrades the third order one. © 2013 IEEE.
- The influence of the substrate bias in Junctionless nanowire transistors(2013-09-06) TREVISOLI, R. D..; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThis work aims at analyzing the influence of the substrate bias in the operation of Junctionless Nanowire Transistors. The analysis is based on simulated and experimental data. The discussion about the substrate influence on the devices operation is also accomplished by modeled results. The threshold voltage and the maximum transconductance dependence on the substrate bias are the key parameters under analysis. © 2013 IEEE.
- «
- 1 (current)
- 2
- 3
- »