Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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6 resultados
Resultados da Pesquisa
- Junctionless nanowire transistors effective channel length extraction through capacitance characteristics(2023-10-05) SILVA, E. M.; TREVISOLI, R.; Rodrigo Doria© 2023 Elsevier LtdThis work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.
- SOI UTBB Capacitive Cross-Coupling Effects in Ultimate Technological Nodes(2022-03-01) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to carry out an analysis of the effects of cross-coupling in a system composed of SOI UTBB MOSFETs in ultimate integration nodes through numerical simulations, validated with experimental data from literature. In this analysis, it could be observed that two devices located on the channel length direction provoke a reduced cross-coupling on each other. For devices located at distances below 50 nm, a capacitive parasitic coupling between the devices can be observed along with the thermal coupling effect.
- A New Method for Series Resistance Extraction of Nanometer MOSFETs(2017-07-05) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; BARRAUD, S.; VINET, M.; CASSE, M.; REIMBOLD, G.; FAYNOT, O.; GHIBAUDO, G.; Marcelo Antonio PavanelloThis paper presents a new method for the series resistance extraction in ultimate MOSFETs using a single drain current versus gate voltage characteristic curve. The method is based on the Y-function curve, such that the series resistance is obtained through the curve of the total resistance as a function of the inverse of the Y-function. It includes both first-and second-order mobility degradation factors. To validate the proposed method, numerical simulations have been performed for devices of different characteristics. Besides, the method applicability has been demonstrated for experimental silicon nanowires and FinFETs. Apart from that, devices with different channel lengths can be used to estimate the mobility degradation factor influence.
- Experimental comparative analysis between junctionless and inversion mode nanowire transistors down to 10 nm-long channel lengths(2018-10-18) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; VINET, M.; CASSE, M.; FAYNOT, O.This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.
- Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model(2019-02-27) MOREIRA, C. V.; TREVISOLI, R.; Marcelo Antonio PavanelloThis paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement.
- Analysis of the Thermal Properties of Self-Cascode Structures Composed by UTBB Transistors(2020) COSTA, F. J.; TREVISOLI, R.; Michelly De Souza; Rodrigo Doria© 2020 IEEE.The focus of this work is to perform an analysis of the thermal properties of the Self-Cascode (SC) structure composed by advanced UTBB SOI MOSFETs under a selected set of back gate biases, through 2D numerical simulations. In this work, it could be observed that the SC structure presents a 50 % lower thermal resistance in comparison with a single device with similar channel length. The application of a back gate bias of 2 V to the drain-sided device or -2 V to the source-sided devices of the SC has shown a decrease of 10-16 % in the thermal resistance.