Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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9 resultados
Resultados da Pesquisa
- Interface traps density extraction through transient measurements in junctionless transistors(2022-08-05) TEICEIRA DA FONTE, E.; TREVISOLI, R.; BARRAUD S.; Rodrigo Doria© 2022 Elsevier LtdThis paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.
- Charge Pumping-Based Method for Traps Density Extraction in Junctionless Transistors(2021) FONTE, E. T.; TREVISOLI, R.; Rodrido Doria© 2021 IEEE.A study of Junctionless Transistors (JNTs) is presented in this work, with emphasis on verifying the extraction of the interface traps density using the charge pumping method. To the best of our knowledge, this is the first work to use this method in JNTs. The method was applied to both simulated and experimental data and has shown satisfactory results.
- Analog operation of junctionless nanowire transistors down to liquid helium temperature(2014-07-09) TREVISOLI, R.; Michelly De Souza; Rodrido Doria; KILCHYTSHA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThe aim of this work is to analyze the analog operation of Junctionless Nanowire Transistors at temperatures down to liquid helium temperature. The analysis is performed in terms of the transconductance, open loop voltage gain and output conductance for experimental long channel devices. It is shown that the temperature reduction can affect significantly the analog performance of the devices. © 2014 IEEE.
- Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K(2014-10-29) TREVISOLI, R.; Michelly De Souza; Rodrido Doria; KILCHTYSKA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThe aim of this work is to analyze the operation of Junctionless Nanowire Transistors at liquid helium temperature, focusing the operation at linear regime. The drain current, the transconductance, the low field mobility, subthreshold slope, the interface trap density and the channel resistance are the key parameters under analysis.
- Improved analog operation of junctionless nanowire transistors using back bias(2015-03-18) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThis work reports, for the first time, an analysis of substrate bias on the analog parameters of Junctionless Nanowire Transistors operating as single transistor amplifiers through experimental and simulated data. The study is performed in terms of output conductance, transconductance, open loop voltage gain and transconductance to the drain current ratio. It has been shown that the substrate bias can affect significantly the performance of junctionless devices, such that the positive back bias can reduce the output conductance and improve the voltage gain.
- Physical insights on the dynamic response of junctionless nanowire transistors(2016-11-02) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThe aim of this work is to present, for the first time, an analysis of the maximum oscillation frequency (fmax) presented by Junctionless Nanowire Transistors (JNTs) as well as its impact and the carriers transit time on the minimum switching time of these devices. It has been observed that despite presenting lower fmax than inversion mode devices, fmax of JNTs is benefited by its lower capacitances along a large interval in its operation range. Also, it has been shown that the transit time can significantly influence on the minimum switching time of long devices, since it can be larger than the minimum oscillation time, what does not occur in shorter JNTs.
- A new series resistance extraction method for junctionless nanowire transistors(2016-11-02) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; BARRAUD, S.; VINET, M.; Marcelo Antonio PavanelloSeries resistance can severely affect the electrical behavior of such Junctionless Nanowire Transistors. The aim of this work is to propose a new method for the extraction of the series resistance in Junctionless Nanowire Transistors. The method is validated by means of tridimensional numerical simulations and experimental results, using transistors with different widths and doping concentrations.
- Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model(2019-02-27) MOREIRA, C. V.; TREVISOLI, R.; Marcelo Antonio PavanelloThis paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement.
- Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors(2019-09-26) TREVISOLI, R.; Rodrigo Doria; BARRAUD, S.; Marcelo Antonio PavanelloThe aim of this work is to propose a compact analytical model for the Low Frequency Noise (LFN) in Junctionless Nanowire Transistors (JNTs). Since JNTs work differently from inversion mode transistors, the noise is also expected to behave differently. To the best of our knowledge, no analytical models have been presented for LFN in these devices. The proposed model is validated through numerical simulations. Experimental results are also used to demonstrate its applicability.