Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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9 resultados
Resultados da Pesquisa
- Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors(2012-03-17) Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode. © 2012 IEEE.
- Simulation of miller OpAmp analog circuit with FinFET transistors(2012-03-17) CONTRERAS, E.; CERDEIRA, A.; Marcelo Antonio PavanelloIn this paper we present a methodology to use the Symmetric Doped Double-Gate Model implemented in Verilog-A to simulate analog circuits with FinFET Technology. A Miller operational Amplifier was simulated in SPICE simulator and the results were validated comparing them with experimental data published in previous works. © 2012 IEEE.
- Fin width influence on uniaxial stress of triple-gate SOI nMOSFETs(2012-03-17) BÜHLER, Rudolf Theoderich; MARTINO, J. A.; AGOPIAN, P. G. D.; Renato GiacominiThis work analyzes the fin width dependence on induced uniaxial stress on n-type MuGFETs thought 3D simulations. A study on the stress distribution and the electric characterization of the device to measure the impact on its performance is accomplished. The stress distribution and the device performance exhibited dependence on the fin width, with higher stress transfer for narrower fins resulting in better electrical performance. © 2012 IEEE.
- Uniaxial mechanical stress influence on the low frequency noise in FD SOI nMOSFETs operating in saturation(2012-03-17) DE SAOUZA, M. A. S.; CLAEYS, C.; Rodrido Doria; Marcelo Antonio Pavanello; SIMOEN, E.This work presents a study of the influence of mechanical stress on the low frequency noise in planar SOI transistors operating in saturation. Several channel lengths were measured, and the results show a reduction of the low frequency noise for strained devices independent of the channel length, and this reduction is more effective for smaller channel lengths. © 2012 IEEE.
- AGSPICE: A new analog ICs design tool based on evolutionary electronics used for extracting additional design recommendations(2012) DE LIMA, MORETO R. A.; THOMAZ, C. E.; Salvador GimenezAnalog integrated circuits (ICs) design is a complex task due to the large number of input variables that must be determined simultaneously in order to achieve different multiple design goals of an analog integrated circuit design, such as voltage gain (A V), unit voltage gain frequency (f T), slew-rate (SR), harmonic distortion (THD), etc. By using an evolutionary system based on Genetic Algorithm (AG) integrated to the SPICE simulator, named AGSPICE, this work aims to study, understand and calculate the different correlations between the MOSFETs inversion regimes and the design goals of an operational transconductance amplifier (OTA) operating in different design features. We believe that the AGSPICE can provide new design recommendations for the designers and reduce the design cycle time as well. Our experimental results with the AGSPICE are also compared to the results obtained manually and present compatible solutions to other works available in the related literature. © 2012 IEEE.
- Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations(2012-03/17) MARINIELLO, G.; Rodrido Doria; Michelly De Souza; Marcelo Antonio Pavanello; TREVISOLI, R. D. G.Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D), fin width (W fin) and fin height (H fin). © 2012 IEEE.
- Drain current model for junctionless nanowire transistors(2012-03-17) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results. © 2012 IEEE.
- An analytical estimation model for the spreading resistance of Double-Gate FinFETs(2012-03-17) MALHEIRO, C. T.; PEREIRA, A. S. N.; Renato GiacominiThe FinFET spreading resistance is the component of the parasitic resistance of FinFETs caused by the curved shape of the current lines in drain and source regions, close to the junctions. This work proposes a very simple analytical model for the spreading resistance of Double-Gate FinFETs that is valid for any fin width from 16nm, without fitting parameters. The model output was compared to data extracted from numeric simulation and it showed accuracy better than 8% for the considered range of devices with three different doping concentrations. © 2012 IEEE.
- Analog performance of submicron GC SOI MOSFETs(2012-03-17) NEMER J. P.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length. © 2012 IEEE.