Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

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Agora exibindo 1 - 10 de 22

Halo effects on 0.13 μm floating-body partially depleted SOI n-Mosfets in low temperature operation
(2003-10-12) MARTINO, J. A.; Marcelo Antonio Pavanello; SIMOEN, E.; CLAEYS, C.
This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation, Parameters such as the Drain Induced Barrier Lowering and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 - 300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature.
Operation of double gate graded-channel transistors at low temperatures
(2003-10-16) Marcelo Antonio Pavanello; MARTINO, J. A.; CHUNG, T. M.; KRANTI, A.; RASKIN, J. P.; FLANDRE, D.
This work studies the use of graded-channel profile on double gate SOI MOSEETs from room temperature down to 95 K with the aim of studying the analog performance. Two-dimensional simulations are performed to provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs. It is demonstrated that double gate graded-channel MOSFETs can provide extremely improved Early voltage, high transconductance and drive current in comparison to the conventional double gate fully depleted SOI MOSFETs with similar dimensions. A degradation in the Early voltage as the temperature decreases has been found but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150 K to 300 K due compensation provided by the transconductance to drain current ratio.
An improved model for the triangular SOI misalignment test structure
(2004-09-07) Renato Giacomini; MARINO, J. A.
The triangular misalignment test structure is an arrangement of MOS transistors to calculate the poly and source/drain diffusion misalignment as a function of drain current differences. Although these structures have non-rectangular shapes, which may be detrimental for the design, the advantage of measuring currents instead of voltage differences make them very useful. This work presents a new analytic misalignment error model for thin-film, fully depleted SOI technology, using non rectangular devices. Three-dimensional numerical simulation is used as a reference for models comparison and verification. These simulation results show that the proposed analytical model presents an improved performance compared to those available in the literature.
Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures
(2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.
An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.
A fully analytical continuous model for graded-channel SOI MOSFET for analog applications
(2004-09-11) Michelly De Souza; Marcelo Antonio Pavanello; INIGUEZ, B.; FLANDRE, D.
In this work an analytical model of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is proposed for analog applications. The model is based on a series association of two conventional SOI nMOSFETs each representing one part of the GC SOI nMOSFET channel. From this assumption, we propose a current model that considers the GC SOI MOSFET as a conventional SOI transistor, represented by one part of the channel only, in which the drain voltage is modulated by the remaining part. The proposed model has been verified through the comparison between its results and experimental measurements, presenting a good agreement. Some important characteristics for analog circuits, such as transconductance and Early voltage, are compared between the model results and experimental curves.
Improved current mirror performance using graded-channel silicon-on-insulator devices in high temperature operation
(2004-09-11) FERREIRA, R. S.; Marcelo Antonio Pavanello
This work studies the output characteristics of analog current mirror using graded-channel in comparison to conventional Silicon-On-Insulator MOSFETs in high temperature operation. The output characteristics are discussed, based on simulation and experimental results. The Mirroring Precision, Output Swing and Output Resistance are extremely improved at high temperature thanks to the reduced output conductance in graded-channel transistors.
Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures
(2004-09-11) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
The use of partially depleted deep-submicrometer SOI nMOSFETs in mixed mode applications is discussed in terms of channel engineering and temperature of operation. It is shown that the halo implantation used to obtain better digital characteristics degrades the gain and the unity gain frequency in comparison to devices that are not subjected to this implantation.
Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures
(2004-09-11) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; MARTINO, J. A.; FLANDRE, D.; RASKIN, J.-P.
This paper presents the behavior of Graded Channel SOI Gate-All-Around (GAA) nMOSFET at high temperatures in the range of 27°C to 300°C. Threshold voltage, subthreshold slope, maximum transconductance, zero temperature coefficient and Early voltage were investigated through three-dimensional simulations and electrical characterization. It was verified that when temperature increases, threshold voltage decreases, subthreshold slope increases and did not suffer any degradation with the LLD/L ratio increase. The maximum transconductance decreases when temperature increases, and increases for larger LLD/L ratios, and Early voltage decreases almost linearly with temperature increase. The results show the excellent behavior of GC SOI GAA nMOSFET at high temperatures compared to conventional SOI GAA devices.
Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMoSFETs
(2005-09-07) Milene Galeti; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
This paper presents an analysis of the gate oxide thickness and temperature influence on the carrier generation lifetime determination. The study is accomplished through two-dimensional numerical simulations in partially depleted SOI nMOSFETs and compared with experimental data of devices fabricated with a 0.13 μm SOI CMOS technology. The temperature varied from 20°C to 80°C and the gate oxide thickness between 1.5 nm and 3.5 nm. Beyond the generation lifetime, other electric parameters were also analyzed as the threshold voltage, the surface potential, the activation energy and the gate current. A reduction of surface potential was observed for an increase in the gate oxide thickness, specially in the steady state surface potential. In the present study, the decrease in gate oxide thickness caused a maximum of 2% variation in the activation energy. For the step bias used, the gate current is not enough large to control the body charging and makes it less sensitive to transient effects.
Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET
(2005-09-05) PAIOLA, A. G.; NICOLETT, A. S.; MARTINO, J. A.
This work analyzes the influence of the gate oxide tunneling current on the extraction of the silicon film and front oxide thickness on deep submicrometer fully depleted SOI nMOSFET devices. Numerical bidimensional simulations to support the analysis and experimental measurements were done using 0.13 μm SOI CMOS technology.

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