Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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9 resultados
Resultados da Pesquisa
- Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures(2022-07-04) CERDEIRA, A.; ESTRADA, M.; DA SILVA, G. M.; RODRIGUES, J. C.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM), previously validated for modeling FinFETs, stacked nanowire, and nanosheet transistors at room temperature, can be extended for modeling stacked nanowire and nanosheet transistors at high temperatures. The modeled results are validated by comparison with experimental data.
- On the compact modelling of Si nanowire and Si nanosheet MOSFETs(2022) CERDEIRA, A.; ESTRADA, M.; Marcelo Antonio PavanelloIn this paper, three-dimensional technology computer aided design simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in nanowire and nanosheet structures, are practically same. This characteristic makes it possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend of the application of the symmetric doped double-gate model (SDDGM) model to nanowires and nanosheets metal-oxide-semiconductor field effect transistors, with no need to include new parameters. The model SDDGM is validated for this application using several measured and simulated structures of nanowires and nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in the SmartSPICE circuit simulator.
- A compact model and an extraction method for the FinFET spreading resistance(2011-09-02) Marcelo Parada; MALHEIRO, C. T.; AGOPIAN, P. G. D.; Renato GiacominiThis work presents a study of the FinFET series resistance focused on the spreading component. A new simple analytical expression is proposed to easily estimate and model this parasitic parameter. The extraction method departs from the drain current versus gate voltage curves of several channel and source/drain lengths. The resistance values extracted from simulated devices are compared to the outputs of the analytic model and a very good agreement is achieved. The proposed model showed accurate estimative for a wider range of devices then previously published models. © The Electrochemical Society.
- Analytical compact model for triple gate junctionless MOSFETs(2015-10-13) HERRERA, F. A.; CERDEIRA, A.; PAZ, B. C.; ESTRADA, M.; Marcelo Antonio PavanelloA new compact analytical model for triple gate junctionless transistors JLT is presented considering the capacitances when the fin height is reduced. For its calculation, the capacitance is separated into gate and silicon height capacitance. On the modeling side, threshold voltage, drain current model and short channel effects are modeled considering the influence of variable fin height. Based on our previous developed analytical model for 2D devices, which neglects the fin height effects, a 3D analytical compact model was developed including short channel effects. The 3D model presented is useful for modeling silicon triple gate junctionless transistors. The model validation is done by simulations varying the fin height and channel length.
- Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range(2018-03-19) CERDEIRA, A.; AVILA-HERRERA, F.; ESTRADA, M.; DORIA, R. T.; Marcelo Antonio PavanelloThis paper presents the necessary adaptions on the proposed compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range. The model validation is performed by comparison against experimental results showing very good agreement, with continuous current and its derivatives in all regions of operation and temperatures.
- Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model(2019-02-27) MOREIRA, C. V.; TREVISOLI, R.; Marcelo Antonio PavanelloThis paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement.
- Analytical Compact Model for Transcapacitances of Junctionless Nanowire Transistors(2021-05-25) Marcelo Antonio Pavanello; Ribeiro T.A.; Cerdeira A.; Avila-Herrera F.This paper presents the proposal of a compact analytical model for the transcapacitances of long-channel triple gate junctionless nanowire transistors. The model is validated using comparisons against 3D TCAD simulations showing very good agreement, with continuous transitions between all regions of operation.
- Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range(2019) Pavanello M.A.; Cerdeira A.; Doria R.T.; Ribeiro T.A.; Avila-Herrera F.; Estrada M.© 2019 Elsevier LtdThis paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.
- Charge-based compact analytical model for triple-gate junctionless nanowire transistors(2016) Avila-Herrera F.; Paz B.C.; Cerdeira A.; Estrada M.; Pavanello M.A.© 2016 Elsevier Ltd.A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D continuous model has been developed, including the dependence of the fin height and the short channel effects. An expression for threshold voltage is presented. The model defines a one-dimensional semiconductor effective capacitance due to the width and the height of the fin, which in turn redefines the potentials and charges, without altering the general modeling procedure. Threshold voltage roll-off, subthreshold slope, DIBL and channel length modulation, as well as, the mobility degradation and the velocity saturation have been introduced into the model. The validation was done by 3-D numerical simulations for different fin heights and channel lengths, as well as, by experimental measurements in nanowire transistors with doping concentrations of 5 × 1018 and 1 × 1019 cm-3. The developed model is suitable for describing the current-voltage characteristics in all operating regions from double-gate to nanowire transistor with only 8 adjusting parameters.