Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
Navegar
80 resultados
Resultados da Pesquisa
- Analog parameters of strained non-rectangular triple gate FinFETs(2010-01-05) BÜHLER, Rudolf Theoderich; Renato Giacomini; MARTINO, J. A.The strained silicon technology together to the reduction of the temperature is studied in this paper on trapezoidal triple gate FinFETs, through three-dimensional numerical simulation, with particular focus on analog parameters. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes demonstrated that, although the strained silicon technology provided higher intrinsic voltage gain, the fin shape can have a major role in analog parameters, helping to improve those parameters under certain circumstances. Higher intrinsic voltage gains were obtained for strained devices with top fin width larger than bottom. ©The Electrochemical Society.
- Applying the diamond layout style for FinFET(2012-12-02) NETO, E. D.; Salvador GimenezThe FinFET devices have been on focus in recent years due its elevated gate control capability over the channel region, what gives this technology a scalability advantage against others. The planar Diamond MOSFET layout, on the other hand, has also shown great results regarding its possible use on integrated circuits applications. In this paper, the concept of the Diamond layout style is extended to its three-dimensional version, the Diamond FinFET. 3D numerical simulations are performed in order to compare the possible advantages and disadvantages between this innovative layout style and its conventional counterpart, keeping the same gate area, geometric factor and bias conditions. It is shown that this new device inherits the qualities of its planar MOSFET version and it is proved that it can reduce significantly the die area of the analog and digital (mixed) low-power low-voltage integrated circuits due to its high capability as current driver. © The Electrochemical Society.
- Impact of halo implantation on the lifetime assessment in partially depleted soi transistors(2006-11-03) Milene Galeti; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.This paper investigates the impact of the presence of a HALO implanted region on the lifetime analysis, based on a study of drain current switch-off transients. The latter were experimentally determined and compared with two-dimensional numerical simulations for PD SOI nMOSFET devices fabricated in a 0.13 μm CMOS technology. This study investigated for different channel lengths the drain current transient in relation with devices parameters such as the body potential, threshold voltage and the current density in the source/drain junctions. In the HALO devices the hole current density through the junctions between source/drain and body were not very significant, so that the influence of the junction is only due to the capacitive coupling between source/body and drain/body channel. For the channel length range studied (from 10 to 0.2μm), the transient time of HALO devices suffers from a 56% reduction. However, in the no HALO devices, there is beyond the capacitive coupling also a significant increase in the hole current density, causing a transient time reduction of 74%, for the same channel length range. copyright The Electrochemical Society.
- Study of the drain leakage current behavior in circular gate SOI nMOSFET using 0.13μm SOI CMOS technology at high temperatures(2007) ALMEIDA, L. M.; BELLODI, M.It is presented numerical tridimensional simulations results concerning to the evolution of the drain leakage current behavior in Circular Gate SOI nMOSFETs operating from room temperature up to 573K. The results show that the leakage current behavior depends strongly on the channel length. Also, it was observed that the leakage current density distribution is non uniform along the silicon film thickness and it depends on the channel length and changes as the temperature goes up. © The Electrochemical Society.
- Sidewall angle influence on the FinFET analog parameters(2007-09-06) Renato Giacomini; MARTINO, J. A.; Marcelo Antonio PavanelloThe width variations along the vertical direction, due to process limitations, that appear in some fabricated FinFETs lead to non-rectangular cross-sectional shapes. One of the most frequent shapes is the trapezoidal (inclined sidewalls). These geometry variations may cause some changes in the device electrical characteristics. This work analyses the influence of the sidewall inclination angle on analog parameters, such as voltage gain, transconductance, output conductance, threshold voltage and also on the corner effects, through 3-D numeric simulation. © The Electrochemical Society.
- Physical characterization and reliability aspects of MuGFETs(2007-09-06) CLAEYS, C.; SIMOEN, E.; RAFI, J. M.; Marcelo Antonio Pavanello; MARTINO, J. A.Multi-gate devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling to the 32 nm and below technology nodes. Worldwide much attention is given to FinFET and MuGFET device architectures. This paper reviews some physical characterization and reliability aspects of such devices. Attention is given to aspects such as transient floating body effects, their performance at both high and low temperatures, gate coupling effects and their low frequency noise behavior. In addition, their potential radiation hardness in view of space applications is outlined. © The Electrochemical Society.
- Influence of the N-type FinFET width on the zero temperature coefficient(2007-09-07) BELLODI, M.; MARTINO, J. A.; CAMILO, L. M.; SIMOEN, E.; CLAEYS, C.This paper presents the influence of the Fin width dimension on the Zero Temperature Coefficient (ZTC) behavior for devices operating at high temperatures (from room temperature up to 573K). Besides this, a simple analytical model is presented in order to describe the ZTC behavior as the temperature increases. Three-dimensional simulations are carried out and compared with experimental results to support the interpretation presented along this work. © The Electrochemical Society.
- Simple analytical model to study the ZTC bias point in FinFETs(2007-05-11) BELLODI, M.; CAMILLO, L. M.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work we present a simple analytical model to study the Zero Temperature Coefficient (ZTC) bias point in FinFETs operating from room temperature up to 573 K. Three-dimensional simulations are carried out and compared with experimental results to qualify the results. © The Electrochemical Society.
- Analysis of matching in graded-channel SOI MOSFETs(2007-09-06) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents an analysis of mismatch in Graded-Channel (GC) SOI MOSFETs. Experimental results show that GC devices present poorer threshold voltage and drain current matching in comparison to conventional SOI counterpart. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to predict the matching behavior both in linear and saturation regions. © The Electrochemical Society.
- Non-vertical sidewall angle influence on triple-gate FinFETs corner effects(2007-05-11) Renato Giacomini; MARTINO J. A.Some fabricated FinFET devices present width variations along the vertical direction due to fabrication process limitations. These variations lead to non-rectangular cross-section shapes. One of the most frequent shapes is the trapezoidal (plane and inclined sidewalls). Another identified phenomenon in multiple-gate devices such as FinFETs is the corner effect, which occurs due to the overlapping of the influences of two gate planes near the device corners. This paper addresses the variation of the corner effect as a function of the sidewall inclination angle, through 3-D numeric simulation. A set of devices of several inclination angles and body doping levels were simulated. The corner effect depends on the inclination angle, specially for higher doping levels. © The Electrochemical Society.