Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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12 resultados
Resultados da Pesquisa
- Global and/or local strain influence on p- and nMuGFET analog performance(2011-01-05) AGOPIAN, P. G. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work, the analog performance is evaluated for tri-gate p-and nMuGFETs processed with and without the implementation of different global or local strain engineering techniques. For n-channel devices, the intrinsic voltage gain showed to be worse for strained devices when the fin is narrow. Only for wider fins the voltage gain increases with the strain efficiency due to mobility enhancement. Besides the voltage gain, the transconductance, output conductance and Early Voltage are also evaluated. In spite of the smaller impact of strain engineering, pMuGFETs show better analog behavior for all studied parameters. ©The Electrochemical Society.
- Impact of proton irradiation on strained triple gate SOI p- and n-MOSFETs(2011-09-23) AGOPIAN, P. G. D.; MARTINO, J. A.; KOBAYASHI, D.; SIMOEN, E.; CLAEYS, C.In this work the proton irradiation influence on basic and analog parameters of triple-gate SOI MOSFETs is investigated. The studied devices are strained and unstrained p- and nMuGFETs. The type of stress considered in each case, was the stress that results in a better performance of p- (CESL) and n-devices (sSOI+CESL). Although the results showed the worse behavior for post-irradiated nMOS transistors, a higher immunity to the back interface influence was obtained for post-irradiated pMOS devices and consequently a better analog performance was observed. The unit gain frequency improved for p and nMOS post-irradiated devices. © 2011 IEEE.
- Uniaxial stress efficiency for different fin dimensions of triple-gate SOI nMOSFETs(2011-10-06) BÜHLER, Rudolf Theoderich; AGOPIAN, P. G. D.; Renato Giacomini; SIMOEN, E.; CLAEYS, C.; MARTINO, J. A.The stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed, leading to the conclusion that the shift in the stress level is too small to cause a pronounced impact on the parameters. On the other hand, the reduction of the silicon fin height showed more interesting results. Despite that the standard device with smaller fin height presented a lower intrinsic voltage gain performance when compared to the reference device, when implementing strain it supersedes the reference device and presented an enhancement in the intrinsic voltage gain over the standard one up to 8 %, larger than the 5.1 % obtained for the reference device. © 2011 IEEE.
- Influence of 60-MeV proton-irradiation on standard and strained n-and p-Channel MuGFETs(2012-01-05) AGOPIAN, P. G. D.; MARTINO, J. A.; KOBAYASHI, D.; SIMOEN. E.; CLAEYS. C.In this work the proton irradiation influence on Multiple Gate MOSFETs (MuGFETs) performance is investigated. This analysis was performed through basic and analog parameters considering four different splits (unstrained, uniaxial, biaxial, uniaxial+biaxial). Although the influence of radiation is more pronounced for p-channel devices, in pMuGFETs devices, the radiation promotes a higher immunity to the back interface conduction resulting in the analog performance improvement. On the other hand, the proton irradiation results in a degradation of the post-irradiated n-channel transistors behavior. The unit gain frequency showed to be strongly dependent on stress efficiency and the radiation results in an increase of the unit gain frequency for splits with high stress effectiveness for both cases p-and nMuGFETs. © 2012 IEEE.
- Uniaxial and/or biaxial strain influence on MuGFET devices(2012-01-05) AGOPIAN, P. G. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work, the impact of global andor local strain engineering techniques on tri-gate p- and nMuGFETs performance is experimentally evaluated. Multiple gate structures were analyzed through basic and analog performance parameters for four different splits processed with different strain-engineering techniques (unstrained, uniaxial, biaxial and uniaxial+biaxial stress). While n-channel devices with narrow fins present a worse analog behavior, biaxial stress promotes the electron mobility for larger devices increasing the voltage gain. Besides the voltage gain, the transconductance, output conductance and Early Voltage are also evaluated. Although pMuGFETs are less affected by the strain engineering, they present better analog behavior for all studied devices. © 2012 The Electrochemical Society.
- Back bias influence on analog performance of pTFET(2013-10-10) AGOPIAN, P. G. D.; NEVES, F. S.; MARTINO, J. A.; VANDOOREN, A.; ROOYACKERS, R.; SIMOEN, E.; CLAEYS, C.In this work the back bias influence on the analog performance of tunnel-FETs is evaluated experimentally for the first time. The analysis of the transconductance, output conductance and intrinsic voltage gain (Av) was performed by comparing the pTFET behavior with a well-known pFinFET that was fabricated using the same process flow. Numerical simulations were also performed in order to explain the pTFET behavior. Although the pTFET shows to be more susceptible to the back bias condition, it also shows to present always a better Av for all bias conditions. The best result in both devices was obtained when the back bias is near 0 V and the Av difference is around 30 dB in favor of pTFET. © 2013 IEEE.
- NW-TFET analog performance for different Ge source compositions(2013-10-10) AGOPIAN, P. G. D.; DOS SANTOS, S. D.; NEVES, F. S.; MARTINO, J. A.; VANDOOREN, A.; ROOYACKERS, R.; SIMOEN, E.; CLAEYS, C.The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain (AV) due to their better output conductance (less drain electric field penetration than for 46%). The Si source NW-TFET presented the worst analog behavior at lower gate bias. However, when VGS increases, smaller is its AV degradation making it equal or better than the value obtained for SiGe source devices, since in the former the Trap Assisted Tunneling (TAT) is predominant. The peculiar NW-TFET low frequency noise behavior is also presented. © 2013 IEEE.
- Experimental comparison between trigate p-TFET and p-FinFET analog performance as a function of temperature(2013-01-05) AGOPIAN, P. G. D.; MARTINO, J. A.; ROOYACKERS, R.; VANDOOREN, A.; SIMOEN, E.; CLAEYS, C.This paper presents, for the first time, the experimental comparison between the p-type trigate FinFET and trigate p-TFET analog performances for devices fabricated on the same wafer. A careful analysis of the electrical characteristics is performed to choose the best bias conditions for the analog comparison between these devices. A higher intrinsic voltage gain is obtained for p-TFET devices because of their better output conductance, which is more than four orders of magnitude better than the one obtained for p-FinFET transistors at the same bias conditions from room temperature up to 150° C. © 1963-2012 IEEE.
- Influence of 45° Substrate Rotation on the Analog Performance of Biaxially Strained-Silicon SOI MuGFETs(2013-05-16) DE SOUZA, M. A. S.; Rodrido Doria; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloIn this work the influence of the substrate rotation on the analog performance of strained SOI MuGFETs is presented. Measurements performed in fabricated devices show a degradation of the maximum transconductance at both linear and saturation regime. The substrate rotation has no influence on the output conductance. The intrinsic voltage gain and the unit gain frequency were extracted and presented a reduction promoted by substrate rotation, being more evident for a narrow fin. © The Electrochemical Society.
- Experimental comparison between pTFET and pFinFET under analog operation(2013) AGOPIAN, P. G. D.; MARTINO, J. A.; ROOYACKERS, R.; VANDOOREN, A.; SIMON, E.; CLAEYS, C.In this work, the analog performance of Tunnel FET and FinFET, which have a different principle of operation, is evaluated based on a comparison between them. This comparison is performed through the drain current behavior, the transconductance, the output conductance and the intrinsic voltage gain. Although the TFET devices present a smaller transconductance than the FinFET ones, the output behavior is strongly improved and results in a better performance of TFET devices when the focus is the intrinsic voltage gain. © The Electrochemical Society.