Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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32 resultados
Resultados da Pesquisa
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
- Analysis of Fin Width Influence on the Carrier's Mobility of Nanowire MOSFETs(2021-08-31) CCOTO, C. U. C.; BERGAMASHI, F. E.; Marcelo Antonio Pavanello©2021 IEEE.In this work, the study of the effective electron mobility (peff) of n-channel MOS transistor nanowires is presented. By extracting the mobility of the top and sidewall using the surface current separation technique together with the split-CV method. Analyzing the comparison of simulated TCAD results and experimental transistors fabricated with various fin widths (12nm-82nm) and how the effect of varying the fin width and applied substrate voltages interfere with carrier mobility values.
- Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors' Mobility Variation Induced by Substrate Bias(2022) BERMAMASCHI, F. E.; RIBEIRO, T. A.; PAZ, B. C.; Michelly De Souza; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 1963-2012 IEEE.This work investigates the carrier mobility variation in Ω-gate silicon-on-insulator (SOI) nanowire MOS transistors induced by substrate (or back) biasing. The analysis is carried out through experimental measurements and 3-D TCAD simulation, performed in n-type devices with variable fin width. Mobility enhancement is observed for lower back bias levels, due to the initial conduction through the Si-BOX interface, which presents higher mobility, prior to the activation of the front channel. As back bias is increased, however, the strong substrate-induced electric field in the back channel (BC) is responsible for worsening scattering mechanisms in the BC, such as surface roughness and acoustic phonon scattering, inducing mobility degradation. The effect is amplified as the fin width increases. For short-channel devices, the use of back bias was more beneficial for mobility due to a stronger mobility enhancement and lower mobility degradation.
- Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures(2022-09-17) Marcelo Antonio Pavanello; Michelly De Souza© 2022, Brazilian Microelectronics Society. All rights reserved.—This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be dis-cussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-In-duced Drain Leakage will also be studied. The experimental re-sults in the whole temperature range confirm that SOI nan-owires are an excellent alternative for FinFET replacement in future technological nodes.
- Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures(2022-07-04) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K and 580 K. The study is conducted using experimental data, corroborated with 3D TCAD simulations. It is demonstrated that the GIDL current normalized by the total fin width is larger in nanosheet MOSFET than for the nanowire at high temperatures. Additionally, the nanosheet device presents a larger variation of the normalized GIDL current with the temperature than the nanowire one.
- Extraction of the Back Channel Mobility in SOI Nanowire MOS Transistors under Substrate Biasing(2022-07-04) BERGAMASHI, F. E.; WIRTH, G. I.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an analysis of the effective mobility of SOI nanowire MOS transistors is performed by separating the mobility of electrons in the back channel, which is created when substrate bias is applied. Measurements are done in n-type devices with an Ω-gate structure and variable channel length. Both longer and shorter channel devices present higher mobility in the back channel, but strong mobility reduction is observed with the increase of the substrate bias, reaching values close to that of the front channel at strong back bias levels. This effect is independent of the applied gate voltage overdrive. Three-dimensional TCAD simulation validates the method used to separate the back channel mobility, showing that the front channel mobility is not changed by the increase in substrate bias.
- Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures(2022-07-04) CERDEIRA, A.; ESTRADA, M.; DA SILVA, G. M.; RODRIGUES, J. C.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM), previously validated for modeling FinFETs, stacked nanowire, and nanosheet transistors at room temperature, can be extended for modeling stacked nanowire and nanosheet transistors at high temperatures. The modeled results are validated by comparison with experimental data.
- Modeling Quantum Confinement in Multi-Gate Transistors with Effective Potential(2022) SOARES, C. S.; BAIKADI, P. K. R.; ROSSETO, A. C. J.; Marcelo Antonio Pavanello; VASILESKA, D.; WIRTH, G. I.© 2022 IEEE.Particle-based Monte Carlo device simulators are an efficient tool to investigate the performance and reliability of transistors. The semiclassical theoretical model employed in the Monte Carlo device simulator is unsuccessful to describe some aspects of the multi-gate transistors that come from the quantum behavior of charge carriers. To take into consideration the space-quantization effects in these simulators, a quantum correction is necessary. We propose to include an effective potential in the Monte Carlo device simulator to address the wave-like behavior of electrons in n-type silicon FinFET and n-type silicon nanowire transistors. The effective potential has a unique parameter, which can be adjusted to find a line density using an Effective Potential-Poisson solver that matches with the line density calculated using a Schrodinger-Poisson solver. We demonstrated that using the effective potential model, the effect of the electron confinement is well described.
- An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires(2022) Michelly De Souza; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.
- Analysis of Variability in Transconductance and Mobility of Nanowire Transistors(2022-08-22) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2022 IEEE.This work presents a comparison between the variability in junctionless nanowire transistors and inversion-mode nanowire transistors, looking at the transconductance, low-field mobility, linear and quadratic mobility degradation coefficients. To extract these parameters, the Y-Function method has been used. The obtained results shows differences in mobility and transconductance matching coefficients, indicating that mobility influence is not the only source of transconductance variation.