Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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8 resultados
Resultados da Pesquisa
- Detailed analysis of transport properties of FinFETs through Y-Function method: Effects of substrate orientation and strain(2015-10-13) RIBEIRO, T. A.; SIMOEN, E.; CLAEYS, C.; MARTINO, J. A.; Marcelo Antonio PavanelloThis paper studies the transport parameters of n-type FinFETs extracted using the Y-Function methodology, by comparing their dependence on the fin width and the crystallographic orientation for standard and rotated substrates as well as the influence of biaxial strain. The Y-Function has been applied with a recursive algorithm to improve its accuracy. The results obtained show that the low-field mobility increases, for devices with narrow fin, just with the rotation of the substrate. With biaxial strain the mobility increases about 50% for the standard devices and about 30% for the rotated devices compared to non-strained devices. The mobility degradation is also extracted and evaluated showing strong coulomb scattering and surface roughness scattering, where the later is higher on standard and strained devices than on only rotated devices.
- Analytical compact model for triple gate junctionless MOSFETs(2015-10-13) HERRERA, F. A.; CERDEIRA, A.; PAZ, B. C.; ESTRADA, M.; Marcelo Antonio PavanelloA new compact analytical model for triple gate junctionless transistors JLT is presented considering the capacitances when the fin height is reduced. For its calculation, the capacitance is separated into gate and silicon height capacitance. On the modeling side, threshold voltage, drain current model and short channel effects are modeled considering the influence of variable fin height. Based on our previous developed analytical model for 2D devices, which neglects the fin height effects, a 3D analytical compact model was developed including short channel effects. The 3D model presented is useful for modeling silicon triple gate junctionless transistors. The model validation is done by simulations varying the fin height and channel length.
- Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures(2015-10-13) Rodrido Doria; FLANDRE, D.; TREVISOLLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThis paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
- Role of the extensions in Double-Gate Junctionless MOSFETs in the drain current at high gate voltage(2015-10-13) CERDEIRA, A.; HERRERA, F. A.; PAZ, B. C.; ESTRADA, M.; Marcelo Antonio PavanelloThis work studies the effect of doping level applied to the extensions on the electrical characteristics of short channel double gate junctionless transistor. Structures with homogeneous doping profile between source and drain contacts and structures with additional doping in the extensions are studied. 2D simulations were performed for structures with doping concentration of 5×1018 and 1019 cm-3, silicon layer thickness of 10 and 15 nm and with/without extensions of 30 nm. Above flat band voltage, the drain current in saturation presents an important decrease for homogeneously doped structures with extensions attributed to the reduction of potentials at high gate voltage. Lower short channel effects, as less threshold voltage roll off and less subthreshold slope take place in this type of structures due to the shift of minimum potential in the extension regions.
- Effect of channel doping concentration on the harmonic distortion of asymmetric n-and p-type self-cascode MOSFETs(2015-09-04) D´OLIVEIRA, L. M.; Rodrido Doria; Marcelo Antonio Pavanello; FLANDRE. D.; Michelly De Souza© 2015 IEEE.This paper compares the harmonic distortion of n-and p-type symmetric (S-SC) and asymmetric self-cascode (A-SC) structures of different channel doping concentrations, providing a physic analysis of its behavior. This study is made by experimental measurements of structures composed by n-and p-type MOSFETs taking the second and third order harmonics as figures of merit. For strong inversion, the normalized second order harmonic distortion was better for the A-SC structures composed by devices with lower channel doping concentration on the transistor near the drain for either n-and p-type composite MOSFETs.
- Asymmetric Self-Cascode versus Graded-Channel SOI nMOSFETs for analog applications(2015-10-13) ASSALTI, R.; Marcelo Antonio Pavanello; FLANDRE, D.; Michelly De SouzaThis paper compares the performance of Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs, both proposed to improve the analog performance of fully depleted SOI nMOSFETs. The differences at device level are evaluated and the impact of their application in basic analog circuits, i.e. common-source amplifier, source-follower and common-source current mirror are explored through experimental results.
- On the origin of low-frequency noise of submicron Graded-Channel fully depleted SOI nMOSFETs(2015-08-31) MOLTO, A. R.; Rodrigo Doria; Michelly De Souza; Marcelo Antonio PavanelloThis paper deals with the Low-Frequency Noise (LFN) behavior of submicron Graded-Channel SOI nMOSFETs, fabricated in a 150 nm Technology from Oki Semiconductors as a continuation from previous works, looking at the noise sources of these devices. The effects of channel length reduction and gate bias dependence on the LFN of devices biased in linear regime are investigated. The effective trap density and the KF constant, which can be used in BSIM SPICE-like models, are determined.
- Effective channel length in Junctionless Nanowire Transistors(2015-10-13) TREVISOLLI, R.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloThe aim of this work is to analyze the influence of the lateral depletion induced by the gate towards the source/drain regions on the effective channel length of Junctionless Nanowire Transistors. The effective channel length increase at the subthreshold regime is analyzed by means of simulations together with experimental results, showing that the JNT can be significantly longer than the gate length.