Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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19 resultados
Resultados da Pesquisa
Artigo 17 Citação(ões) na Scopus Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion(2011-09-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C.-W.; FERAIN, I.; AKHAVAN, N. D.; YAN, R.; RAZAVI, P.; YU, R.; FRANTI, A.; COLINGE, J-P.This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.Artigo 54 Citação(ões) na Scopus Impact of the series resistance in the I-V characteristics of junctionless nanowire transistors and its dependence on the temperature(2012-01-05) Rodrigo Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe effect of the source/drain parasitic resistance (R S) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on R S has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.- Analysis of Variability in Transconductance and Mobility of Nanowire Transistors(2022-08-22) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2022 IEEE.This work presents a comparison between the variability in junctionless nanowire transistors and inversion-mode nanowire transistors, looking at the transconductance, low-field mobility, linear and quadratic mobility degradation coefficients. To extract these parameters, the Y-Function method has been used. The obtained results shows differences in mobility and transconductance matching coefficients, indicating that mobility influence is not the only source of transconductance variation.
- Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures(2022-08-22) PRATES, R. R.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work aims to present the electrical properties of junctionless and inversion-mode nanowires MOSFETs in the temperature range from 300 K to 580 K. Devices with different fin widths are compared. The comparison is performed using experimental data looking for some of the fundamental electrical parameters of these transistors such as threshold voltage, inverse subthreshold slope, current, and carrier mobility over the temperature.
- Variability Modeling in Triple-Gate Junctionless Nanowire Transistors(2022-01-05) TREVISOLI, R.; Marcelo Antonio Pavanello; Rodrigo Doria; CAPOVILLA, C.E.; BARRAUD, S.; Michelly De SouzaIEEEThis work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.
- Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors(2022-01-05) RIBEIRO, T. A.; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; Marcelo Antonio PavanelloThis work performs a pragmatic evaluation of the different junctionless devices architectures with channel lengths down to 30 nm on their electrical characteristics. By adopting multiple combinations between the fin height (HFIN) and the fin width (WFIN), chosen from the range of published data in the literature, the devices will operate from double-gate (FinFET like) mode towards to nanowire mode. Additionally, junctionless transistors with and without additional doping at the drain and source extensions were studied. Experimentally calibrated 3D TCAD simulations are used to allow for the study of these several combinations. Results show that for long-channel devices the best performance is obtained for tall and narrow fins, leading to the highest on-to-off current ratio (ION/IOFF) and the smallest values of subthreshold swing and DIBL. On the other hand, for short channel devices, independently of the doping level of the extensions, the best results are found for short HFIN and narrow WFIN, leading to the smaller values of subthreshold swing and DIBL, with a high ION/IOFF ratio. However, the use of doped extensions degrades the overall device performance of short-channel junctionless devices as will be demonstrated.
- Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors(2012-01-05) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; DAS, S.; FERAIN, I.; Marcelo Antonio PavanelloThis paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model. © 2012 IEEE.
- Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations(2012-03/17) MARINIELLO, G.; Rodrido Doria; Michelly De Souza; Marcelo Antonio Pavanello; TREVISOLI, R. D. G.Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D), fin width (W fin) and fin height (H fin). © 2012 IEEE.
- Drain current model for junctionless nanowire transistors(2012-03-17) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results. © 2012 IEEE.
- Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors(2012-10-04) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; FERAIN, I.; DAS, S.; Marcelo Antonio PavanelloMulti-gate architecture has been considered as one of the most viable alternatives to MOS devices scaling below 22 nm nodes [1] due to its stronger robustness to the short channel effects with respect to planar architectures. In short channel devices, the control of the gate over the channel charges dramatically decreases making the use of planar devices extremely challenging. Despite providing an improved coupling between gates and channel, conventional inversion mode (IM) multi-gate structures such as Trigate and FinFETs present p-n junctions between source/drain and channel, which can become an important bottleneck for ultimate technologies in which the formation of ultra-sharp junctions is needed in order to avoid the source/drain dopants diffusion into the channel. A novel multi-gate architecture so-called Junctionless Nanowire Transistor (JNT) was recently developed to overcome this bottleneck [2-3]. The JNT consists of a silicon nanowire surrounded by gate stack and is different from multi-gate IM devices due to its doping profile which is heavy and constant between source, channel and drain without any dopant gradients. The longitudinal sections of both a pMOS and an nMOS JNT are shown in Fig. 1 where the p-type is doped with boron and the n-type ones with phosphorous. The silicon nanowire needs to have a square-section small enough to be fully depleted at low gate voltages, turning off the device. Above threshold, the current flows mainly due to bulk conduction [4]. Several papers have shown the potentiality of the JNT for technological nodes beyond 10 nm [2-6] since it provides better DIBL, subthreshold slope and analog properties than IM multi-gate transistors of similar dimensions [5,6]. Although the Low-Frequency Noise (LFN) of JNTs has been treated in different papers [7,8], only long devices have been evaluated up to now and in none of them the LFN of pMOS was addressed as proposed in the current paper. © 2012 IEEE.