Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
Navegar
14 resultados
Resultados da Pesquisa
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
Artigo 17 Citação(ões) na Scopus Thin-film lateral SOI pin diodes for thermal sensing reaching the cryogenic regime(2010-09-01) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.Artigo 4 Citação(ões) na Scopus Fin cross-section shape influence on short channel effects of mugfets(2012-05-05) BUHLER, R. T.; Giacomini R.; Marcelo Antonio Pavanello; Joao Antonio MartinoMultiple-gate FETs is normally constructed on pre-etched silicon fins. These devices often present casual width variations along the silicon height; mostly caused by technological limitations of the fin definition process, due to non-ideal anisotropic etch. The resulting devices have, consequently, non-rectangular cross-sections, which can affect their electrical behavior. This work addresses the dependence of fin width non-uniformity on the occurrence of short-channel effects through comparative analysis, based on threedimensional numeric simulation of non-rectangular cross-section devices. The influence of the fin crosssection shape on electrical parameters showed to be dependent on channel length, becoming more sensible to the fin shape as the channel length is reduced, with better DC performance present on devices with bottom fin width smaller than top fin width due to the higher transconductance and lower output conductance, resulting on higher intrinsic voltage gain. For opposite fin shapes the total gate capacitance present higher values, beneficiating AC analog parameters, such as unit gain frequency.- An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires(2022) Michelly De Souza; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.
- Reliability performance characterization of SOI FinFets(2009-06-02) CLAEYS, C.; PUT, S.; RAFI, J. M.; Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.FinFET devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling CMOS to 22 nm and below. Some physical characterization and reliability aspects of these devices are reviewed. Attention is given to transient floating body effects and low frequency noise, which may yield information on the materials' characteristics like carrier recombination lifetime or interface and oxide trap density. These methods can be useful to study the performance of these components under harsh operation conditions of low or high temperature, or at high bias voltages. ©2009 IEEE.
- Low frequency noise in submicron Graded-Channel SOI MOSFETs(2013-09-06) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThe origin of the low-frequency noise in submicron fully depleted Graded-Channel (GC) SOI MOSFET is investigated in terms of the channel length comparing two different technologies, OKI semiconductors and UCL. © 2013 IEEE.
- On the origin of low-frequency noise of submicron Graded-Channel fully depleted SOI nMOSFETs(2015-08-31) MOLTO, A. R.; Rodrigo Doria; Michelly De Souza; Marcelo Antonio PavanelloThis paper deals with the Low-Frequency Noise (LFN) behavior of submicron Graded-Channel SOI nMOSFETs, fabricated in a 150 nm Technology from Oki Semiconductors as a continuation from previous works, looking at the noise sources of these devices. The effects of channel length reduction and gate bias dependence on the LFN of devices biased in linear regime are investigated. The effective trap density and the KF constant, which can be used in BSIM SPICE-like models, are determined.
- Low power highly linear temperature sensor based on SOI lateral PIN diodes(2017) Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This work presents a highly linear temperature sensors implemented with SOI Lateral PIN Diodes, for low-power applications, biased on the exponential region of the I-V characteristics. Experimental results are shown for temperatures ranging between 150 K and 400 K, showing that depending on the selected bias currents, the linearity can be improved in comparison to a single SOI PIN diode. Simulations results show that the sensing range can be extended for both lower and higher temperatures maintaining high linearity.
- New method for individual electrical characterization of stacked SOI nanowire MOSFETs(2017-10-18) PAZ, B.C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloA new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Q-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C.
- Cryogenic operation of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs(2018-03-19) PAZ, B. C.; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; VINET, M.; FAYNOT, O.This work evaluates the operation of p-type Si0.7Ge0.3-on-insulator (SGOI) nanowires from room temperature down to 5.2K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Results show oscillations in both transconductance and gate to channel capacitance curves for temperatures smaller than 50K and fin width of 20nm due to quantum confinement effects. Improvement on the effective mobility for SGOI in comparison to SOI nanowires is still observed for devices with fin width scaled down to 20nm. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and SOI nanowires.