Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

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Agora exibindo 1 - 10 de 11

Study of matching properties of graded-channel SOI MOSFETs
(2008-01-05) Michelly De Souza; FLANDRE, D.; Marcelo Antonio Pavanello
In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to validate the model-based analysis both in linear and saturation regions.
Thin-film lateral SOI pin diodes for thermal sensing reaching the cryogenic regime
(2010-09-01) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio Pavanello
This paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.
Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion
(2011-09-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C.-W.; FERAIN, I.; AKHAVAN, N. D.; YAN, R.; RAZAVI, P.; YU, R.; FRANTI, A.; COLINGE, J-P.
This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.
Temperature and silicon film thickness influence on the operation of lateral SOI PIN photodiodes for detection of short wavelengths
(2011-09-05) Michelly De Souza; BULTEEL, O.; FLANDRE, D.; Marcelo Antonio Pavanello
This work presents an analysis of the temperature influence on the performance of a lateral thin-film SOI PIN photodiodes when illuminated by low wavelengths, in the range of blue and ultra-violet (UV). Experimental measurements performed from 100K to 400K showed that the optical responsitivity of SOI PIN photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations showed the same trends as in the experimental results, and were used both to investigate the physical phenomena responsible for the observed behavior as a function of the temperature as well as to predict the influence of silicon film thickness downscaling on the photodetector performance.
Impact of the series resistance in the I-V characteristics of junctionless nanowire transistors and its dependence on the temperature
(2012-01-05) Rodrigo Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio Pavanello
The effect of the source/drain parasitic resistance (R S) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on R S has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.
Modeling of thin-film lateral SOI PIN diodes with an alternative multi-branch explicit current model
(2012-01-05) LUGO-MUNOZ; MUCI, J.; ORTIZ-CONDE, A.; GARCIA-SANCHEZ, F. J.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio Pavanello
We propose the use of an alternative multi-exponential model to describe multiple conduction mechanisms in thin-film SOI PIN diodes with parasitic series resistance over a wide operating temperature range, from 90 to 390 K. This alternative multi-exponential model can be used for semiconductor junctions which exhibit multiple conduction mechanisms with series and shunt resistances. Using Thevenin's theorem and the Lambert W function, the terminal current is expressed explicitly as a function of the terminal voltage. Its explicit nature allows higher computational efficiency and makes this model better suited for repetitive simulation applications than conventional implicit models. Additionally, direct analytic differentiation and integration are possible. This alternative model is used to describe the I-V characteristics of real SOI PIN diodes.
Drain current and short channel effects modeling in junctionless nanowire transistors
(2013-01-05) TREVISOLI, R. D.; Rodrigo Doria; Michelly De Souza; Marcelo Antonio Pavanello
© 2013, Brazilian Microelectronics Society. All rights reserved.Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.
The roles of the gate bias, doping concentration, temperature and geometry on the harmonic distortion of junctionless nanowire transistors operating in the linear regime
(2014-05-05) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; ESTRADA, M.; CERDEIRA, A.; Marcelo Antonio Pavanello
© 2014, Journal of Integrated Circuits and Systems 2014. All rights received.The linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature, the doping concentration and the geometry on the overall linearity have been evaluated. The increase of the series resistance associated both to the variation of the physical parameters and the incomplete ionization effect has shown to improve the second order distortion and degrade the third order one.
Origin of the low-frequency noise in the asymmetric self-cascode structure composed by fully depleted SOI nMOSFETs
(2017-08-05) ASSALTI, R.; Rodrigo Doria; FLANDRE, D.; Michelly De Souza
© 2017, Brazilian Microelectronics Society. All rights reserved.In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure is linked to carrier number fluctuations, being governed by the noise generated in the transistor near the source. Larger channel doping concentrations degrade the quality of the Si-SiO2 interface and the gate oxide, which causes an increase of the normalized drain current noise spectral density, just as the reduction of the gate voltage overdrive, since there are few carriers in the channel. The A-SC structures have showed higher noise compared with single transistors. In saturation regime, the increase of the gate voltage overdrive has incremented the corner frequency, shifting the g-r noise to higher frequencies. Besides that, the normalized noise has been significantly increased when compared with the linear regime due to the rise of the drain current noise spectral density.
Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures
(2022-09-17) Marcelo Antonio Pavanello; Michelly De Souza
© 2022, Brazilian Microelectronics Society. All rights reserved.—This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be dis-cussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-In-duced Drain Leakage will also be studied. The experimental re-sults in the whole temperature range confirm that SOI nan-owires are an excellent alternative for FinFET replacement in future technological nodes.

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