Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
Navegar
10 resultados
Resultados da Pesquisa
- Comparative Analysis of Transcapacitances in Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs(2022-07-04) ALVES, C. R.; D'OLIVEIRA, L. M.; Michelly De Souza© 2022 IEEE.This work presents a comparative study of the transcapacitances of asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs, by means of two-dimensional numerical simulations. Simulated results show that the gate-to-drain capacitance is smaller for the ASC SOI device if compared to the GC SOI device, despite of the applied VDS.
- Graded-channel SOI nMOSFET model valid for harmonic distortion evaluation(2006-05-17) Michelly De Souza; Marcelo Antonio Pavanello; CERDEIRA, A.; FLANDRE, D.In this paper an evaluation of the harmonic distortion of graded-channel SOI nMOSFETs is performed. The analysis is carried out by comparing an analytical continuous model and experimental results. The total harmonic distortion, as well as the third and second order terms are used as figures of merit in this comparison. It is shown that GC SOI devices present better gain and linearity behavior than conventional devices and that these advantages are well described by the proposed analytical model. The results show that the proposed set of equations is able to describe the linearity behavior of GC devices, indicating its potential to be used in analog circuit simulation and design. © 2006 IEEE.
- Monte Carlo simulation of graded-channel fully depleted SOI nMOSFETs(2011-02-11) MARTIN M. J.; RENGEL R.; GALEOTE J. M.; Michelly De Souza; Marcelo Antonio PavanelloIn this paper a Monte Carlo investigation of Graded Channel (GC) Silicon-On-Insulator MOSFETs is presented. The influence of the length of the lightly-doped region of the channel (LLD) on the microscopic transport properties is exhaustively analyzed. Result show that increasing LLD provides an enhancement of the device performance in terms of drain current and transconductance. However, for LLD values larger than half of the channel the benefits are minimized from a microscopic point of view due to the increasing tendency of the device to behave as a lightly doped conventional transistor. This suggests the existence of an optimum L LD value to fully benefit from the improvements provided by GC doping techniques. © 2011 IEEE.
- Liquid helium temperature operation of graded-channel SOI nMOSFETs(2012-09-02) Michelly De Souza; KILCHYTSHA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThis work reports, for the first time, the operation of Graded-Channel SOI nMOSFETs at liquid helium temperature. As expected, for all measured devices it has been observed that at 4.2K the transconductance increases with respect to room temperature as a consequence of the mobility rise. On the opposite hand, all the studied devices demonstrated a degradation of the output conductance with temperature reduction. However, this degradation is attenuated below 90K. As a consequence, an increase of the Early voltage and of the intrinsic voltage gain were obtained, in contrast to the data reported in the literature, for devices operating down to 100K. It is demonstrated that GC SOI presented larger Early voltage increase at 4.2K than at room temperature. The rise of the voltage gain promoted by GC architecture has shown to be constant with temperature down to 4.2K. © The Electrochemical Society.
- Low frequency noise in submicron Graded-Channel SOI MOSFETs(2013-09-06) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThe origin of the low-frequency noise in submicron fully depleted Graded-Channel (GC) SOI MOSFET is investigated in terms of the channel length comparing two different technologies, OKI semiconductors and UCL. © 2013 IEEE.
- Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias(2014-10-29) ASSALTI, R.; Marcelo Antonio Pavanello; FLANDRE, D.; Michelly De SouzaThis work assesses the analog performance of Graded-Channel FD SOI nMOSFET transistors regarding the dependence of gate voltage overdrive over the length of lightly doped region which maximizes the intrinsic voltage gain, unit gain frequency and breakdown voltage. It is shown that the optimum length of lightly doped region depends on the target application of GC devices.
- Asymmetric Self-Cascode versus Graded-Channel SOI nMOSFETs for analog applications(2015-10-13) ASSALTI, R.; Marcelo Antonio Pavanello; FLANDRE, D.; Michelly De SouzaThis paper compares the performance of Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs, both proposed to improve the analog performance of fully depleted SOI nMOSFETs. The differences at device level are evaluated and the impact of their application in basic analog circuits, i.e. common-source amplifier, source-follower and common-source current mirror are explored through experimental results.
- On the origin of low-frequency noise of submicron Graded-Channel fully depleted SOI nMOSFETs(2015-08-31) MOLTO, A. R.; Rodrigo Doria; Michelly De Souza; Marcelo Antonio PavanelloThis paper deals with the Low-Frequency Noise (LFN) behavior of submicron Graded-Channel SOI nMOSFETs, fabricated in a 150 nm Technology from Oki Semiconductors as a continuation from previous works, looking at the noise sources of these devices. The effects of channel length reduction and gate bias dependence on the LFN of devices biased in linear regime are investigated. The effective trap density and the KF constant, which can be used in BSIM SPICE-like models, are determined.
- Experimental evaluation of mismatching on the analog characteristics of GC SOI MOSFETs(2017-07-28) ALVES, C. R.; Marcelo Antonio Pavanello; Michelly De Souza; FLANDRE, D.This paper presents an experimental study of mismatching on the analog characteristics of fully-depleted graded-channel SOI MOSFET in comparison to uniformly doped transistors. The study is carried out using dedicated structures to account for the mismatch that have been fabricated at the same chip and with the same technology. Important basic parameters such as threshold voltage and subthreshold slope were analyzed as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.
- Numerical simulation and analysis of transistor channel length and doping mismatching in GC SOI nMOSFETs analog figures of merit(2018-08-31) ALVES, C. R.; Michelly De Souza; FLANDRE, D.© 2018 IEEE.This paper presents a two-dimensional numerical simulation study of mismatching on the analog characteristics of fully-depleted graded-channel (GC) SOI MOSFET. The study aims at identifying the mismatching sources that affect the analog performance of GC SOI transistors. The simulations were performed imposing length and doping concentration variations and analyzing its impact on important electrical parameters such as threshold voltage and subthreshold slope, as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.