Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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9 resultados
Resultados da Pesquisa
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
Artigo 17 Citação(ões) na Scopus Thin-film lateral SOI pin diodes for thermal sensing reaching the cryogenic regime(2010-09-01) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.- High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs(2023-01-05) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Pavanello M. A.AuthorIn this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.
- An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires(2022) Michelly De Souza; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.
- Low frequency noise in submicron Graded-Channel SOI MOSFETs(2013-09-06) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThe origin of the low-frequency noise in submicron fully depleted Graded-Channel (GC) SOI MOSFET is investigated in terms of the channel length comparing two different technologies, OKI semiconductors and UCL. © 2013 IEEE.
- On the origin of low-frequency noise of submicron Graded-Channel fully depleted SOI nMOSFETs(2015-08-31) MOLTO, A. R.; Rodrigo Doria; Michelly De Souza; Marcelo Antonio PavanelloThis paper deals with the Low-Frequency Noise (LFN) behavior of submicron Graded-Channel SOI nMOSFETs, fabricated in a 150 nm Technology from Oki Semiconductors as a continuation from previous works, looking at the noise sources of these devices. The effects of channel length reduction and gate bias dependence on the LFN of devices biased in linear regime are investigated. The effective trap density and the KF constant, which can be used in BSIM SPICE-like models, are determined.
- Low power highly linear temperature sensor based on SOI lateral PIN diodes(2017) Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This work presents a highly linear temperature sensors implemented with SOI Lateral PIN Diodes, for low-power applications, biased on the exponential region of the I-V characteristics. Experimental results are shown for temperatures ranging between 150 K and 400 K, showing that depending on the selected bias currents, the linearity can be improved in comparison to a single SOI PIN diode. Simulations results show that the sensing range can be extended for both lower and higher temperatures maintaining high linearity.
- Strategy for Simulation of Analog Circuits with GCSOI MOSFET using BSIM SOI model(2021-04-21) DA SILVA, LUCAS MOTA BARBOSA; Michelly De Souza© 2021 IEEE.This work presents a simulation strategy to simulate Graded-Channel SOI MOSFET electrical characteristics using BSIM SOI SPICE model. The use of uniformly doped transistor model is possible by adjusting low field mobility, degradation mobility factors and parameters related to channel length modulation and DIBL effects. A good agreement with experimental data was achieved at device level. The simulation strategy is validated through the simulation of common-source current mirrors using adjusted SPICE model parameters, presenting the same trends of experimental results available in the literature.
- Analysis of Mobility in Graded-Channel SOI Transistors aiming at Circuit Simulation(2020-07-31) SILVA, LUCAS MOTA BARBOSA DA; PAZ, BRUNA CARDOSO; Michelly De SouzaThis work presents an analysis of the behavior of the effective mobility of graded-channel FD SOI transistors us-ing an Y-Function-based technique. Low field mobility, linear and quadratic attenuation factors were extracted from two-di-mensional numerical simulations. The influence of the length of both channel regions over these parameters was analyzed. The parameters extracted from experimental data were used in a SPICE simulator, showing that it is possible to simulated GC SOI MOSFET using a regular SOI MOSFET model, by adjust-ing its parameters. This approach presents a percentage error smaller than 7.91% for low VDS.