Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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19 resultados
Resultados da Pesquisa
Artigo 17 Citação(ões) na Scopus Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion(2011-09-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C.-W.; FERAIN, I.; AKHAVAN, N. D.; YAN, R.; RAZAVI, P.; YU, R.; FRANTI, A.; COLINGE, J-P.This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.Artigo 54 Citação(ões) na Scopus Impact of the series resistance in the I-V characteristics of junctionless nanowire transistors and its dependence on the temperature(2012-01-05) Rodrigo Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe effect of the source/drain parasitic resistance (R S) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on R S has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.Artigo 8 Citação(ões) na Scopus Drain current and short channel effects modeling in junctionless nanowire transistors(2013-01-05) TREVISOLI, R. D.; Rodrigo Doria; Michelly De Souza; Marcelo Antonio Pavanello© 2013, Brazilian Microelectronics Society. All rights reserved.Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.- Analog operation of junctionless transistors at cryogenic temperatures(2010-10-14) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C. W.; FERAIN, I.; DEHDASHTI AKHAVAN, N.; YAN, R.; RAZAVI, P.; YU, R.; KRANTI, A.; COLINGE, J. P.
- The roles of the electric field and the density of carriers in the improved output conductance of junctionless nanowire transistors(2011-01-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C. W.; FERAIN, I.; DEHDASHTI AKHAVAN, N.; YAN, R.; RAZAVI, P.; YU, R.; KRANTI, A.; COLINGE, J. P.This paper evaluates the roles of the electric field (E) and the density of carries (n) in the drain conductance of Junctionless Nanowire Transistors (JNTs). The behavior of E and n presented by JNTs with the variation of the gate and the drain voltages has been compared to the one presented by Inversion Mode (M) Trigate devices of similar dimensions. It has been shown that the lower drain output conductance exhibited by Junctionless transistors with respect to the IM ones is correlated not only to the differences in the mobility and its degradation but also to the electric field, the density of carries and the first order derivative of these variables with respect the drain voltage. ©The Electrochemical Society.
- Stress relaxation empirical model for biaxially strained triple-gate devices(2011-01-05) TREVISOLI, R. D.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; PAVANELLO, M. A.Multiple gate devices provides short channel effects reduction, been considered promising for sub 20 nm era. Strain engineering has also been considered as an alternative to the miniaturization due to the boost in the carrier mobility. The stress non-uniformity in Multiple gate devices cannot be easily considered in a TCAD device simulation without the coupled process simulation which is a cumbersome task. This work analyses the use of an analytical function to compute accurately the dependence of the strain on the device dimensions. The maximum transconductance gain and the threshold voltage shift are used as key parameters to compare simulated and experimental data. ©The Electrochemical Society.
- Analytical model for the threshold voltage in junctionless nanowire transistors of different geometries(2011-09-02) TREVISOLI, R. D.; Rodrigo Doria; Marcelo Antonio PavanelloJunctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era. As these devices have a constant doping profile from source to drain, they have a great scalability without the need for rigorously controlled doping and activation techniques. These devices also present a flexible threshold voltage, which strongly depends on the device cross section. This work proposes an analytical model for JNTs. The model is derived from the solution of the Poisson equation with the appropriate boundary conditions. The quantum confinement for devices of reduced dimensions has also been accounted. The threshold voltage in cylindrical and trigate JNTs are analyzed. Tridimensional numerical simulations were performed to validate the model. ©The Electrochemical Society.
- Analysis of the low-frequency noise of junctionless nanowire transistors operating in saturation(2011-10-06) Rodrigo Doria; TREVISOLI, R. D.; Michelly De Souza; COLINGE, J.P.; Marcelo Antonio PavanelloThis work presented the LF noise behavior of nMOS JNTs investigated by experimental results. It was shown that JNTs can present either 1/f or 1/f 2 noises, depending on their operation region and the frequency. 1/f noise has been associated to carrier number fluctuations whereas 1/f 2 can be related to defects in the depletion layer. The W mask reduction degrades S Id at higher V GT (∼ 1 V) and present negligible influence on S Id at lower V GT (∼ 0.2 V). © 2011 IEEE.
- Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors(2012-01-05) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; DAS, S.; FERAIN, I.; Marcelo Antonio PavanelloThis paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model. © 2012 IEEE.
- Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements(2012-09-02) MARINIELLO, G.; Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire transistors have been recently proposed as an alternative to overcome the short channel effect caused by the reduction of the transistors dimensions. These devices behave like a gated resistor due to the lack of the p-n junctions in the channel/ source and channel/drain regions. The influence of doping concentration, silicon width, silicon height and gate oxide thickness on the intrinsic gate capacitances are presented in this paper by using three-dimensional numerical simulations and experimental results of fabricated devices. Also the influence of the applied drain bias in the components of the intrinsic gate capacitances is addressed. © The Electrochemical Society.