Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

Navegar

Resultados da Pesquisa

Agora exibindo 1 - 10 de 37

Analysis of silicon thickness reduction on analog parameters of GC GAA SOI transistors operating up to 300°C
(2006-09-01) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; Joao Antonio Martino
This paper analyzes the impact of silicon film thickness reduction in some analog parameters of Gate-All-Around (GAA) transistors using the graded-channel (GC) architecture. The study was done at high temperatures (up to 300°C) through two-dimensional simulations. As the silicon film is reduced an improvement on the Early voltage was observed. However, for GC GAA devices this improvement is more pronounced at room temperature than at high temperatures. The output swing voltage (Vos) was also studied and it decreases while reducing the silicon thickness. Regarding the GC GAA the Vos is larger than conventional GAA in 50 nm thick transistors. © 2006 The Electrochemical Society.
Early voltage behavior in circular gate SOI nMOSFET using 0.13 μm partially-depleted SOI CMOS technology
(2006-09-01) Salvador Gimenez; FERREIRA, R. M. G.; Joao Antonio Martino
This paper studies the Early voltage behavior in circular gate partially-depleted SOI nMOSFET. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Drain current comparisons with rectangular gate partially-depleted SOI nMOSFET are performed, regarding the same effective channel length and width. Experimental results and three-dimensional simulations are used to qualify the results. © 2006 The Electrochemical Society.
Channel length reduction influence on harmonic distortion of graded-channel gate-all-around devices
(2006-09-01) Rodrigo Doria; Marcelo Antonio Pavanello; CERDEIRA, A.; RASKIN, J. P.; FLANDRE, D.
This work compares the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices for analog operation as in an amplifier when the channel length is scaled. The study has been performed through two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar bias the performance of GC GAA transistors remains better than the uniformly doped GAA for any channel length. Although scaling the devices tends to degrade the harmonic distortion, significant results were obtained for the GC configuration measured as an improvement of more than 15 dB in total harmonic distortion-to-gain ratio operating in the same region with channel length of 1uμm and with lightly doped region length of 0.3 μm. © 2006 The Electrochemical Society.
Analysis of self-heating effect in graded-channel silicon-on-insulator nMOSFETs
(2007-08-28) COSTA, S. E. DE S.; Marcelo Antonio Pavanello; Joao Antonio Martino
This paper presents a Self-Heating (SH) analysis using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis is performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations are performed in both studies considering the lattice heating. The models and the thermal conductive constant used in these simulations are also presented. It is demonstrated that GC devices with the same mask channel length presents similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel length, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. © 2006 The Electrochemical Society.
Influence of the tunneling gate current on C-V curves
(2006-08-28) RODRIGUE, M.; SONNENBERG, V.; Joao Antonio Martino
This paper presents a study of the tunneling gate current influence on the Capacitance vs. Voltage curve in deep submicrometer CMOS technology. Two-dimensional numerical simulations are performed considering thin gate oxide and N+ polysilicon as a gate material. The influence of the tunneling gate current on the polysilicon depletion region is also analysed. It is observed that the tunneling current masks the polysilicon depletion effect due to the large increase of the substrate silicon depletion region. © 2006 The Electrochemical Society.
Influence of non-vertical sidewall on finfet threshold voltage
(2006-08-28) Renato Giacomini; Joao Antonio Martino
The FinFET structure is one of the most promising architecture approaches to double-gate devices. Due to limitations of process uniformity, most fabricated FinFETs have width variation along the vertical direction, resulting in non-vertical sidewalls. The impact of non-vertical sidewalls on the threshold voltage of FinFETs is studied in this work through three-dimensional simulation. The main purpose of this study is to verify the applicability of some analytical models developed to double-gate devices with parallel gates to FinFETs with inclined sidewalls. The behavior of the threshold voltage for different doping levels and silicon film width is discussed. The use of the existing models taking an average width of the silicon film as the device width is proposed and shows to be a good approximation. © 2006 The Electrochemical Society.
Series resistance influence on the linear kink effect in twin-gate partially depleted SOI nMOSFETs
(2007-09-01) DER AGOPIAN, P. G.; Joao Antonio Martino; SIMOEN, E.; CLAEYS, C.
This work elaborates on the influence of the series resistance on the linear kink effect (LKE) in twin-gate partially depleted (PD) Silicon-on-Insulator (SOI) nMOSFETs. The study is based on two-dimensional numerical simulations and is validated by experimental results. A relationship between the total resistance and the apparent mobility degradation factor is reported, showing that the twin-gate structure and a conventional SOI transistor with an external resistance both present a similar LKE reduction, The asymmetric behavior of the body potential with the interchange of the master and slave transistor of the twin-gate structure will be also shown. © 2006 The Electrochemical Society.
Charge-based continuous explicit equations for the transconductance and output conductance of submicron graded-channel SOI mosfet's
(2006-09-01) Michelly De Souza; Marcelo Antonio Pavanello
This paper presents charge-based continuous explicit equations for the transconductance and output conductance of submicron Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. Short-channel effects like channel length modulation, velocity saturation and drain-induced barrier lowering have been considered in the proposed expressions. Experimental results were used to test the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement as well as smooth transitions between the different regions of operation, validating the proposed equations. © 2006 The Electrochemical Society.
Impact of halo implantation on the lifetime assessment in partially depleted soi transistors
(2006-11-03) Milene Galeti; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
This paper investigates the impact of the presence of a HALO implanted region on the lifetime analysis, based on a study of drain current switch-off transients. The latter were experimentally determined and compared with two-dimensional numerical simulations for PD SOI nMOSFET devices fabricated in a 0.13 μm CMOS technology. This study investigated for different channel lengths the drain current transient in relation with devices parameters such as the body potential, threshold voltage and the current density in the source/drain junctions. In the HALO devices the hole current density through the junctions between source/drain and body were not very significant, so that the influence of the junction is only due to the capacitive coupling between source/body and drain/body channel. For the channel length range studied (from 10 to 0.2μm), the transient time of HALO devices suffers from a 56% reduction. However, in the no HALO devices, there is beyond the capacitive coupling also a significant increase in the hole current density, causing a transient time reduction of 74%, for the same channel length range. copyright The Electrochemical Society.
Study of the drain leakage current behavior in circular gate SOI nMOSFET using 0.13μm SOI CMOS technology at high temperatures
(2007) ALMEIDA, L. M.; BELLODI, M.
It is presented numerical tridimensional simulations results concerning to the evolution of the drain leakage current behavior in Circular Gate SOI nMOSFETs operating from room temperature up to 573K. The results show that the leakage current behavior depends strongly on the channel length. Also, it was observed that the leakage current density distribution is non uniform along the silicon film thickness and it depends on the channel length and changes as the temperature goes up. © The Electrochemical Society.

Engenharia Elétrica

Navegar

Filtros

Configurações

Ordenar por

Resultados por página

Resultados da Pesquisa