Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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10 resultados
Resultados da Pesquisa
- Junctionless nanowire transistors effective channel length extraction through capacitance characteristics(2023-10-05) SILVA, E. M.; TREVISOLI, R.; Rodrigo Doria© 2023 Elsevier LtdThis work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
- Interface traps density extraction through transient measurements in junctionless transistors(2022-08-05) TEICEIRA DA FONTE, E.; TREVISOLI, R.; BARRAUD S.; Rodrigo Doria© 2022 Elsevier LtdThis paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.
- Cross-coupling effects in common-source current mirrors composed by UTBB transistors(2022) JOSÉ DA COSTA, F.; TREVISOLI, R.; Rodrigo Doria© 2022 Elsevier LtdThis work performs an analysis of the cross-coupling effects influence on the performance of current mirrors composed by advanced UTBB SOI MOSFETs through 3D numerical simulations validated to experimental data of single devices. It is shown the presence of a capacitive coupling acting in the system, which can be demonstrated through the threshold voltage reduction at small distances between devices. Additionally, the temperature rise in the system due to the thermal coupling provokes a decrease in the input current as the devices become closer to each other. This is responsible for an increase of 3 % on ID2/ID1 ratio when the devices are biased at the same time and when the distance between them is lowered to 100 nm.
- Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K(2022-08-05) MARINIELLO, G.; BARRAUD, S.; VINET, M.; CASSE, M.; FAYNOT, O.; CALCADE, J.; Marcelo Antonio Pavanello© 2022 Elsevier LtdThis paper aims at analyzing the electrical characteristics of n-type vertically stacked nanowires with variable fin width, operating in the temperature range of 300–600 K. Basic electrical parameters, such as threshold voltage, subthreshold slope, and carrier mobility are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation, to access some of device's analog figures of merit. Also, it has been analyzed the DIBL, GIDL, Ion, and Ioff. currents.
- Electrical characterization of stacked SOI nanowires at low temperatures(2022-05-05) RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio PavanelloThis work presents the electrical characterization of 2-level vertically stacked nanowire MOSFETs with variable fin widths in the temperature range from 93 K to 400 K. The basic electrical properties, such as threshold voltage, subthreshold slope, and carrier mobility are examined in the linear region with low VDS. In sequence, certain analog figures of merit such as the transconductance, the output conductance, and the voltage gain are assessed in saturation. The threshold voltage variation with temperature is linear and slightly increases for wider devices, which was satisfactorily validated by an analytical model for 3D devices. Additionally, the subthreshold slope remains close to the theoretical limit in the whole range of temperatures. The intrinsic voltage gain is weakly temperature-sensitive in the studied range regardless of the fin width. On the other hand, it increases for narrow devices in all temperatures.
- Analog characteristics of n-type vertically stacked nanowires(2021) MARINIELLO, G.; CARVALHO, C. A. B. D.; CARDOSO, PAZ, B.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2021This paper presents the fundamental analog figures of merit, such as the transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and harmonic distortion (or non-linearity), of n-type vertically stacked nanowires with variable fin width and channel length. To have a physical insight on the results, the basic electrical parameters such as threshold voltage, subthreshold slope and low field electron mobility of the analyzed transistors were also studied. The studied analog parameters are presented in function of the transconductance over drain current, to allow for the comparison at the same inversion level.
- Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures(2021-11-21) RIBEIRO, T. A.; BERGAMASCHI, F.E.; BARRAUD, S.; Marcelo Antonio PavanelloThis work studied the effects of the fin width variation on Silicon-on-Insulator Junctionless Nanowire Transistors (JNTs) working in the temperature range of 300 K to 500 K. The effects of the temperature on the measured drain current and gate capacitance, and on the extracted electrical parameters such as the threshold voltage, the subthreshold slope, and the electron mobility were analyzed. Results show that JNTs with larger fin width may present better carrier mobility at a higher temperature than narrow ones as the degradation due to phonon scattering is decreased and the impurity scattering becomes more relevant. It is demonstrated that JNTs with narrow fin width show higher phonon scattering and higher mobility variation with the temperature than wider ones.
- Thermal cross-coupling effects in side-by-side UTBB-FDSOI transistors(2021-11-05) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2021 Elsevier LtdThe focus of this work is to perform a first-time analysis of the thermal cross-coupling of a device on a neighbor one in advanced UTBB transistors through 3D numerical simulations, validated with experimental data from the literature. In this work, it could be observed that the temperature rise due to a self-heated device can affect the performance of a neighbor one according to the distance between them and to the bias conditions. By varying the distance of the devices from 1 µm to 50 nm, it is shown an influence of the temperature rise due to a self-heated device in threshold voltage, subthreshold swing and in the maximum transconductance as well an increase in the thermal resistance of a neighbor device.
- Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors(2021-12-05) GRAZIANO, N.; COSTA, F. J.; TREVISOLI, R.; BARRAUD, S.; Rodrigo Doria© 2021 Elsevier LtdThis paper deals with the behavior of degradation by NBTI effect in pMOS junctionless nanowire transistors (JNTs). The analysis has been performed through measurements followed by 3D numerical simulations and has shown that the increase in the oxygen precursors density close to the interface leads to the reduction of the saturation in the NBTI effect when the devices operate in partial depletion regime. Such effect can be associated to the change in the flatband voltage to more negative values as well as the threshold voltage with the increase in the precursor density. In the sequence of the work, it was shown that, as the operation temperature rises, there is an increase in the degradation of the threshold voltage due to NBTI, which is more pronounced for larger gate voltages. It was concluded that this effect could be associated to the increase in the recombination rate with the temperature, which enables the occupation of a larger amount of traps.