Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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24 resultados
Resultados da Pesquisa
- Harmonic distortion in symmetric and asymmetric self-cascodes of UTBB FD SOI planar MOSFETs(2019-08-05) D'OLIVEIRA, L. M.; KILCHYTSKA, V.; FLANDRE, D.; Michelly De Souza© 2019 IEEE.This paper presents an analysis of the harmonic distortion extracted from simulated results of symmetric and asymmetric self-cascode devices (S-SC and A-SC, respectively) composed by ultra-thin body and BOX fully depleted silicon-on-insulator planar MOSFETs 28 nm technological node. The results show that the A-SC effectively increases the operating drain current range for lower distortion. Comparisons with the literature show that the A-SC structures are a promising option for enhancing the circuit design flexibility for advanced MOSFETs.
- Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs(2023-01-04) ALVES, C. R.; Michelly De Souza© 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.This work presents a comparative study of the transcapacitances of an asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs with different gate lengths. This analysis was done by means of two-dimensional numerical simulations. Simulated results show the influence of others transcapacitances on the gate-to-gate capacitance for the ASC SOI device and the GC SOI device.
- Comparative Analysis of Transcapacitances in Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs(2022-07-04) ALVES, C. R.; D'OLIVEIRA, L. M.; Michelly De Souza© 2022 IEEE.This work presents a comparative study of the transcapacitances of asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs, by means of two-dimensional numerical simulations. Simulated results show that the gate-to-drain capacitance is smaller for the ASC SOI device if compared to the GC SOI device, despite of the applied VDS.
- Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors(2013-09-06) DE SOUZA, M.; FLANDRE. D.; Marcelo Antonio PavanelloThis paper presents an experimental analysis of channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors. It is shown that the increase of the drain current and transconductance is more pronounced with the reduction of the length of the transistor close to the source (L1), and, differently from the symmetric self-cascode, suffers little influence of the length close to the drain (L2). On the contrary, the output conductance of symmetric and asymmetric threshold voltage structures is benefited by the increase of L 2 and L1, although the asymmetric structure may offer a reduction of up to one order of magnitude in comparison to the symmetric one. It results in larger intrinsic voltage drain for asymmetric devices. This increase has shown to reach more than 20 dB for similar dimensions, or allow for dimension reduction without intrinsic gain degradation. © 2013 IEEE.
- Analysis of Capacitances in Asymmetric SelfCascode SOI nMOSFETs(2021-08-27) ALVES, C.R.; D' OLIVEIRA, L. M.; Michelly De Souza©2021 IEEE.This work presents a study of the capacitance of asymmetric self-cascode silicon-on-insulator (ASC SOI) MOSFETs with similar gate areas and different gate lengths. Experimental results of total gate capacitance of different ASC are presented and complemented with the results of twodimensional simulations. The transcapacitances are explored through two-dimensional simulations. Results show that different channel lengths of the composite transistors have more influence in the depletion region of the capacitance curves for low VDS. The gate-source and gate-drain capacitances show opposite trends with the change in the lengths of source and drain transistors, despite of the VDS applied.
- Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs(2012-10-04) Michelly De Souza; KILCHTYSKA, V.; FLANDRE, D.; Marcelo Antonio PavanelloFully Depleted (FD) SOI technology is well known to provide improved analog performance of CMOS transistors [1, 2]. However, FD SOI transistors may suffer from parasitic bipolar effects (PBE) that cause the degradation of the output conductance [3]. The use of cascode transistors with common gate (making a self-cascode-SC topology) has been shown to reduce the output conductance of MOSFETs, while keeping some advantages of long-channel transistors [4]. Fig. 1 represents the self-cascode transistor, composed by transistors MS and MD, with channel lengths LS and LD, and threshold voltages VT, S and VT, D, respectively (with VT, S = VT, D in the symmetric SC-S-SC). Recent works [5, 6] showed that the use of different threshold voltages (VT) for MS and MD (so-called asymmetric self-cascode-A-SC) is able to further enhance the analog properties of SC n-and pMOS transistors, in comparison to the S-SC, at room temperature (RT). In this paper the enhanced analog performance of asymmetric SC structure is experimentally demonstrated at deep cryogenic environments emphasizing its capability to minimize (or even suppress) PBE in FD SOI n-and p-type MOSFETs at liquid helium temperature (LHT), where this effect is more pronounced [7]. © 2012 IEEE.
- Asymmetric self-cascode FD SOI nMOSFETS harmonic distortion at cryogenic temperatures(2014-07-09) D'OLIVEIRA, L. M.; Rodrido Doria; Marcelo Antonio Pavanello; Michelly De Souza; KILCHYTSHA, V.; FLANDRE, D.This paper presents an analysis on the linearity of Asymmetric Self-Cascode (A-SC) of FD SOI nMOSGET transistors at cryogenic temperatures. This is achieved by evaluating experimental results of associations of transistors with various combinations of channel doping, obtained at temperatures ranging between liquid helium temperature (LHT, 4K) and room temperature (300K). It has been observed that A-SC presents better analog characteristics than the Symmetric Self-Cascode (S-SC) even at temperatures below 100K. The results show improved harmonic distortion at cryogenic temperatures and for structures composed by transistors with lower channel doping. © 2014 IEEE.
- Analysis of harmonic distortion of asymmetric self-cascode association of SOI nMOSFETs operating in saturation(2014-01-20) D'OLIVEIRA, L. M.; Rodrigo Doria; Marcelo Antonio Pavanello; Michelly De Souza; FLANDRE, D.This paper presents an experimental analysis of the harmonic distortion of asymmetric self-cascode (A-SC) association of SOI transistors. This goal is achieved by comparing the A-SC to the symmetric self-cascode (S-SC) configuration with different channel lengths. The non-linearity data have been obtained by applying the Integral Function Method to experimental measurements, for the evaluation of the total and third-order harmonic distortion. The results show that the asymmetric self-cascode provides lower total harmonic distortion than S-SC for all studied channel length associations. If a target distortion level is fixed, the A-SC enables an increase of input signal amplitude. On the other hand, smaller input signal amplitude and distortion are verified in the A-SC when fixing the output amplitude.
- Effect of high temperature on analog parameters of Asymmetric Self-Cascode SOI nMOSFETs(2014-10-29) D'OLIVEIRA, L. M.; FLANDRE, D.; Marcelo Antonio Pavanello; Michelly De SouzaThis paper presents an analysis on the high temperature operation of Silicon-on-Insulator (SOI) nMOSFETs in Asymmetric Self-Cascode (A-SC) configuration. For this analysis, experimental results in the range of 300K to 500K of A-SC structures with different channel lengths for both the drain side transistor (MD) and source side transistor (MS) are used. The effect of varying channel length under high temperatures on the A-SC association is evaluated using as figure of merit important analog parameters, such as the intrinsic voltage gain and transconductance over drain current ratio.
- Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures(2015-10-13) Rodrido Doria; FLANDRE, D.; TREVISOLLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThis paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
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