Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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Resultados da Pesquisa
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
Artigo 8 Citação(ões) na Scopus Study of matching properties of graded-channel SOI MOSFETs(2008-01-05) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to validate the model-based analysis both in linear and saturation regions.- Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures(2022-09-17) Marcelo Antonio Pavanello; Michelly De Souza© 2022, Brazilian Microelectronics Society. All rights reserved.—This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be dis-cussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-In-duced Drain Leakage will also be studied. The experimental re-sults in the whole temperature range confirm that SOI nan-owires are an excellent alternative for FinFET replacement in future technological nodes.
- Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs(2023-01-04) ALVES, C. R.; Michelly De Souza© 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.This work presents a comparative study of the transcapacitances of an asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs with different gate lengths. This analysis was done by means of two-dimensional numerical simulations. Simulated results show the influence of others transcapacitances on the gate-to-gate capacitance for the ASC SOI device and the GC SOI device.
- New Hybrid Generation of Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs(2022-01-05) GALEMBECK, E. H. S.; Salvador GimenezIEEEIt is known that the hexagonal (Diamond) layout style is capable of boosting the electrical performance and ionizing radiation tolerances of metal-oxide-semiconductor field-effect-transistors (MOSFETs). In order to further improve the figures of merit of these devices, it was proposed a hybrid gate geometry that is an evolution of the hexagonal layout style, entitled Half-Diamond. This innovative layout style is able to generate the same electrical effects that the Diamond is able to generate, and it is innovative because it is capable of further reducing the effective channel lengths of MOSFETs implemented with Diamond and rectangular layout styles. Thus, this work describes a comparative study by 3-D numerical simulations data and experimental data between the MOSFETs implemented with the Half-Diamond and Conventional layout styles. The main results found have indicated that the saturation drain current and transconductance of MOSFET layouted with Half-Diamond are 36% and 27% higher, respectively, than those measured in the Conventional MOSFET. Other results have shown that the innovative half-diamond layout style (HDLS) for MOSFETs is capable of reducing the dissipated electrical power in approximately 62% and, therefore, it is an alternative hardness-by-design strategy to remarkably improve complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) energy efficiency. Besides, the electrical behaviors of longitudinal corner effect (LCE), parallel connection of MOSFETs with different channel lengths effect (PAMDLE), and deactivation of parasitic MOSFETs in the bird's beak regions effect (DEPAMBBRE) of the MOSFETs implemented with the HDLS are studied in detail to justify the results found.
- Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs(2006-04-26) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; RASKIN, J. P.; FLANDRE, D.In this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and Gate-All-Around architecture, operating as an amplifier, is studied in terms of lightly doped region length. The total harmonic distortion and third-order harmonic distortion are used as figures of merit. The results are compared with single-gate transistors with similar channel configuration. It is demonstrated that double-gate GC transistors at the same operation region and with similar channel configuration can present up to 20 dB less total harmonic distortion while presenting small third-order harmonic distortion. Considering similar bias voltage, the alternate component of the input sinusoidal signal of GC double-gate devices can be increased by about 200 mV to provide similar third-order harmonic distortion maintaining similar improvements of 20 dB on the total harmonic distortion. © 2006 IEEE.
- Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors(2012-03-17) Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode. © 2012 IEEE.
- Single event effect: Simulations and analysis on 3N163 PMOS transistor(2018-03-18) OLIVEIRA, J.; Marcilei Aparecida Guazzelli; ASSIS, M. A.; Renato Giacomini© 2018 IEEE.This work addresses the simulation of a commercial p-channel MOSFET (3N163) using Sentaurus TCAD tool to observe the behavior of this device operating under heavy-ion environment, in order to study Single Event Effect (SEE) mechanisms and its effects. The simulated results were used to understand experimental data collected on field and make a comparison between real and simulated data. It also allowed interpretation of experimental data, as well as elimination of spurious noises and artifacts, which are not related to SEE effects, but are imposed by environment and experimental facilities.
- Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires(2020-09-01) MARINELLO, GENARO; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAZ, BRUNA CARDOSO; Marcelo Antonio PavanelloThis paper aims at analyzing the analog characteristics of n-type vertically stacked nanowires with 2 channels, varying the fin width and channel length. The basic electrical parameters such as threshold voltage and subthreshold slope are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation.
- On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks(2021-01-05) Michelly De Souza; DORIA, R.T.; TREVISOLI, R.; BARRAUD, S.; Marcelo Antonio PavanelloIn this work an evaluation of analog building blocks using junctionless nanowire transistors is presented. This analysis has been carried out through experimental measurements of junctionless nMOS transistors configured as two amplifier stages composed by single transistors, namely the common-source and the common-drain amplifiers. The performance of junctionless devices is evaluated as a function of channel length, nanowire width, doping concentration and bias condition, taking as figures of merit the voltage gain, linearity and, in the case of the common drain amplifier, the input voltage range. The obtained results indicate that these two basic analog blocks can be benefitted by the use of junctionless devices, providing nearly ideal voltage gain when configured as common-drain amplifier, and improvement on voltage gain and linearity with device narrowing in the case of the common-source amplifier.