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URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
Artigo 17 Citação(ões) na Scopus Thin-film lateral SOI pin diodes for thermal sensing reaching the cryogenic regime(2010-09-01) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.Artigo 4 Citação(ões) na Scopus Fin cross-section shape influence on short channel effects of mugfets(2012-05-05) BUHLER, R. T.; Giacomini R.; Marcelo Antonio Pavanello; Joao Antonio MartinoMultiple-gate FETs is normally constructed on pre-etched silicon fins. These devices often present casual width variations along the silicon height; mostly caused by technological limitations of the fin definition process, due to non-ideal anisotropic etch. The resulting devices have, consequently, non-rectangular cross-sections, which can affect their electrical behavior. This work addresses the dependence of fin width non-uniformity on the occurrence of short-channel effects through comparative analysis, based on threedimensional numeric simulation of non-rectangular cross-section devices. The influence of the fin crosssection shape on electrical parameters showed to be dependent on channel length, becoming more sensible to the fin shape as the channel length is reduced, with better DC performance present on devices with bottom fin width smaller than top fin width due to the higher transconductance and lower output conductance, resulting on higher intrinsic voltage gain. For opposite fin shapes the total gate capacitance present higher values, beneficiating AC analog parameters, such as unit gain frequency.- High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs(2023-01-05) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Pavanello M. A.AuthorIn this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.
- Ultra-Low-Power Diodes Composed by SOI UTBB Transistors(2022-07-04) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to present an analysis of the performance of Ultra-Thin-Body and Buried Oxide transistors working as Ultra-Low-Power diodes. The implementation of different ground planes and substrate biases are analyzed. It is shown a reduced leakage current and increased ratio between the on and off-state currents for the Ultra-Low-Power diode with the N-substrate biased at -2V. However, this condition results in increased threshold voltage. The ground planes do not provoke a significant change in the leakage current, but a noticeable variation can be observed in the ratio between the on and off-state currents due to the higher threshold voltage in relation to the system without ground plane.
- An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires(2022) Michelly De Souza; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.
- Standard MOS Diodes Composed by SOI UTBB Transistors(2022-08-05) COSTA, F. J.; TREVISOLI, R.; CAPOVILLA, C. E.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to present an analysis of the performance of UTBB SOI transistors working as standard diodes, where the implementation of ground planes and substrate bias are analyzed. It is shown a reduced leakage current and increased ratio between the on and off-state currents with the substrate bias at -2 V and with a P-type GP implemented. However, both conditions result in increased threshold voltage.
- SOI UTBB Capacitive Cross-Coupling Effects in Ultimate Technological Nodes(2022-03-01) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to carry out an analysis of the effects of cross-coupling in a system composed of SOI UTBB MOSFETs in ultimate integration nodes through numerical simulations, validated with experimental data from literature. In this analysis, it could be observed that two devices located on the channel length direction provoke a reduced cross-coupling on each other. For devices located at distances below 50 nm, a capacitive parasitic coupling between the devices can be observed along with the thermal coupling effect.
- Cross-coupling effects in common-source current mirrors composed by UTBB transistors(2022) JOSÉ DA COSTA, F.; TREVISOLI, R.; Rodrigo Doria© 2022 Elsevier LtdThis work performs an analysis of the cross-coupling effects influence on the performance of current mirrors composed by advanced UTBB SOI MOSFETs through 3D numerical simulations validated to experimental data of single devices. It is shown the presence of a capacitive coupling acting in the system, which can be demonstrated through the threshold voltage reduction at small distances between devices. Additionally, the temperature rise in the system due to the thermal coupling provokes a decrease in the input current as the devices become closer to each other. This is responsible for an increase of 3 % on ID2/ID1 ratio when the devices are biased at the same time and when the distance between them is lowered to 100 nm.
- Threshold voltages of SOI MuGFETs(2008-12-05) de Andrade M.G.C.; Martino J.A.The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. © 2008 Elsevier Ltd. All rights reserved.
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