Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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18 resultados
Resultados da Pesquisa
Artigo de evento 1 Citação(ões) na Scopus Channel length reduction influence on harmonic distortion of graded-channel gate-all-around devices(2006-09-01) Rodrigo Doria; Marcelo Antonio Pavanello; CERDEIRA, A.; RASKIN, J. P.; FLANDRE, D.This work compares the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices for analog operation as in an amplifier when the channel length is scaled. The study has been performed through two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar bias the performance of GC GAA transistors remains better than the uniformly doped GAA for any channel length. Although scaling the devices tends to degrade the harmonic distortion, significant results were obtained for the GC configuration measured as an improvement of more than 15 dB in total harmonic distortion-to-gain ratio operating in the same region with channel length of 1uμm and with lightly doped region length of 0.3 μm. © 2006 The Electrochemical Society.- Analysis of matching in graded-channel SOI MOSFETs(2007-09-06) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents an analysis of mismatch in Graded-Channel (GC) SOI MOSFETs. Experimental results show that GC devices present poorer threshold voltage and drain current matching in comparison to conventional SOI counterpart. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to predict the matching behavior both in linear and saturation regions. © The Electrochemical Society.
- Application of double gate graded-channel SOI in MOSFET-C balanced structures(2007-05-11) Rodrigo Doria; Marcelo Antonio Pavanello; CERDEIRA, A.; RASKIN J. P.; FLANDRE, D.This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices when applied in 2-MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive. © The Electrochemical Society.
- Impact of graded-channel SOI MOSFET application on the performance of Cascode and Wilson current mirrors(2007-09-06) FLANDRE, D.; Marcelo Antonio PavanelloThis work shows the impact of the use of graded-channel SOI MOSFETs (GC) in Wilson and Cascode current mirrors. The study was made through bi-dimensional simulations and experimental measurements, focusing on the mirroring precision, the output swing voltage (VOS) and output resistance of each architecture comparing with the conventional SOI devices. It was observed that the devices of graded-channel (GC) presented some improvement in the mirroring precision and a significant increase in the output resistance and output swing in all the architectures studied if compared to standard fully depleted SOI MOSEET. the setting time of GC current mirrors has been Also studied and has demonstrated improvements in relation to conventional SOI devices. © The Electrochemical Society.
- Channel length influence on the performance of source-follower buffers implemented with graded-channel SOI nMOSFETs(2008-09-04) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThis work presents an evaluation of the influence of channel length on the performance of graded-channel (GC) SOI nMOSFETs operating as source-follower buffers. Experimental data is used to compare the buffer gain and linearity of GC and standard SOI nMOS transistors for different mask channel lengths and similar effective channel length. Two-dimensional numerical simulations were also performed, showing that the gain of buffers implemented with GC devices remains close to the theoretical limit even when short-channel devices are used. The simulated results indicate that the length of a source-follower buffer using GC devices can be reduced by a factor of 5, in comparison with the standard counterpart, without gain degradation or linearity worsening. © The Electrochemical Society.
- Linearity analysis in double gate Graded-Channel SOI devices applied to 2-MOS MOSFET-C balanced structures(2008-09-04) Rodrigo Doria; CERDEIRA, A.; RASKIN, J. P.; FLANDRE, D.; Marcelo Antonio PavanelloThis paper examines the linearity of 2-MOS MOSFET-C balanced structures using conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices. The distortion analysis has been performed through the evaluation of third order harmonic distortion (HD3). The study has been carried out through experimental results, two-dimensional process and device simulations. Along this work, the best operation bias in terms of HD3 is determined for each analysed device and the couple device that exhibits lower HD3 is pointed out. The use of GC GAA devices in 2-MOS structures has showed to improve the linearity in relation to the conventional GAA. Finally, a discussion over the non-linearities causes is performed clarifying their origins and the improvement provided by the adoption of GC GAA devices in 2-MOS structures. © The Electrochemical Society.
- On the performance of thin-film lateral SOI PIN diodes as thermal sensors in a wide temperature range(2009-09-03) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents a study of lateral SOI PIN diodes as temperature sensors in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend this analysis, verifying the accuracy of the existing model. © The Electrochemical Society.
- Analytical modeling of double gate graded-channel SOI transistors for analog applications(2009-05-29) FERREIRA, F. A. L. P.; CERDEIRA, A.; FLANDRE, D.; Marcelo Antonio PavanelloIn this work we present the development of an analytical model for double gate (DG) Silicon-on-Insulator (SOI) nMOSFET transistor with graded-channel (GC), valid from weak inversion to strong inversion. Atlas numerical two-dimensional simulations and experimental results are used to validate the proposed model. Good agreement between simulated, modeled and experimental results is demonstrated. ©The Electrochemical Society.
- Performance of common-source, Cascode and Wilson current mirrors implemented with graded-channel SOI nMOSFETs in a wide temperature range(2009-05-29) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThis work presents an experimental comparative analysis of the behavior of current mirrors implemented with standard uniformly doped and Graded-Channel (GC) SOI nMOSFETs as a function of the temperature. Three different current mirror architectures were used, Common-source, Wilson and Cascode. The experimental results show that the use of Graded-Channel transistors promotes not only the increase of the output swing, but also the increase of the output resistance in all evaluated architectures, in comparison to the standard uniformly doped counterpart. Despite some degradation observed with the temperature reduction, current mirrors with GC transistors still present better performance than those implemented with standard SOI transistors. ©The Electrochemical Society.
- Analysis of lateral SOI PIN diodes for the detection of blue and UV wavelengths in a wide temperature range(2010-01-05) Michelly De Souza; BULTEEL, O.; FLANDRE, D.; Marcelo Antonio PavanelloThis work presents an analysis on the performance of lateral thin-film SOI PIN diodes for the detection of short wavelengths, in the range of blue and ultra-violet (UV) wavelengms, as a function of the temperature, reaching the cryogenic regime. Measurements performed for temperatures ranging from 100 K to 400 K showed mat the optical responsitivity of these photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations were performed showing the same trends as the experimental data, and were used to predict the influence of silicon film thickness downscaling on me photodetector performance. ©The Electrochemical Society.