Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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74 resultados
Resultados da Pesquisa
Artigo de evento 1 Citação(ões) na Scopus Halo effects on 0.13 μm floating-body partially depleted SOI n-Mosfets in low temperature operation(2003-10-12) MARTINO, J. A.; Marcelo Antonio Pavanello; SIMOEN, E.; CLAEYS, C.This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation, Parameters such as the Drain Induced Barrier Lowering and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 - 300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature.Artigo de evento 1 Citação(ões) na Scopus Operation of double gate graded-channel transistors at low temperatures(2003-10-16) Marcelo Antonio Pavanello; MARTINO, J. A.; CHUNG, T. M.; KRANTI, A.; RASKIN, J. P.; FLANDRE, D.This work studies the use of graded-channel profile on double gate SOI MOSEETs from room temperature down to 95 K with the aim of studying the analog performance. Two-dimensional simulations are performed to provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs. It is demonstrated that double gate graded-channel MOSFETs can provide extremely improved Early voltage, high transconductance and drive current in comparison to the conventional double gate fully depleted SOI MOSFETs with similar dimensions. A degradation in the Early voltage as the temperature decreases has been found but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150 K to 300 K due compensation provided by the transconductance to drain current ratio.Artigo de evento 0 Citação(ões) na Scopus Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures(2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.Artigo de evento 1 Citação(ões) na Scopus Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures(2004-09-11) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.The use of partially depleted deep-submicrometer SOI nMOSFETs in mixed mode applications is discussed in terms of channel engineering and temperature of operation. It is shown that the halo implantation used to obtain better digital characteristics degrades the gain and the unity gain frequency in comparison to devices that are not subjected to this implantation.Artigo de evento 1 Citação(ões) na Scopus Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures(2004-09-11) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; MARTINO, J. A.; FLANDRE, D.; RASKIN, J.-P.This paper presents the behavior of Graded Channel SOI Gate-All-Around (GAA) nMOSFET at high temperatures in the range of 27°C to 300°C. Threshold voltage, subthreshold slope, maximum transconductance, zero temperature coefficient and Early voltage were investigated through three-dimensional simulations and electrical characterization. It was verified that when temperature increases, threshold voltage decreases, subthreshold slope increases and did not suffer any degradation with the LLD/L ratio increase. The maximum transconductance decreases when temperature increases, and increases for larger LLD/L ratios, and Early voltage decreases almost linearly with temperature increase. The results show the excellent behavior of GC SOI GAA nMOSFET at high temperatures compared to conventional SOI GAA devices.Artigo de evento 1 Citação(ões) na Scopus On-resistance and harmonic distortion in graded-channel SOI FD MOSFET(2004-11-05) CERDEIRA, A.; ALEMAN, M. A.; Marcelo Antonio Pavanello; MARTINO, J. A.; VANCAILLIE, L.; FLANDRE, D.In this paper we analyze the advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The study of the two major figures of merit in such applications, i.e. on-resistance and non-linear harmonic distortion, is supported by measurements on conventional and Graded-Channel (GC) fully depleted (FD) SOI MOSFETs. The quasi linear I-V characteristics of GC transistors demonstrate a decrease of the on-resistance as the length of the low doped region into the channel is augmented and an improvement of the third order harmonic distortion (HD3), when compared with conventional transistors. A full comparison method between conventional and GC SOI MOSFETs is presented considering HD3 evolution with on-resistance tuning under low voltage of operation, demonstrating the significant advantages of the asymmetrical long channel transistors. © 2004 IEEE.Artigo de evento 1 Citação(ões) na Scopus Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMoSFETs(2005-09-07) Milene Galeti; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.This paper presents an analysis of the gate oxide thickness and temperature influence on the carrier generation lifetime determination. The study is accomplished through two-dimensional numerical simulations in partially depleted SOI nMOSFETs and compared with experimental data of devices fabricated with a 0.13 μm SOI CMOS technology. The temperature varied from 20°C to 80°C and the gate oxide thickness between 1.5 nm and 3.5 nm. Beyond the generation lifetime, other electric parameters were also analyzed as the threshold voltage, the surface potential, the activation energy and the gate current. A reduction of surface potential was observed for an increase in the gate oxide thickness, specially in the steady state surface potential. In the present study, the decrease in gate oxide thickness caused a maximum of 2% variation in the activation energy. For the step bias used, the gate current is not enough large to control the body charging and makes it less sensitive to transient effects.Artigo de evento 0 Citação(ões) na Scopus Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET(2005-09-05) PAIOLA, A. G.; NICOLETT, A. S.; MARTINO, J. A.This work analyzes the influence of the gate oxide tunneling current on the extraction of the silicon film and front oxide thickness on deep submicrometer fully depleted SOI nMOSFET devices. Numerical bidimensional simulations to support the analysis and experimental measurements were done using 0.13 μm SOI CMOS technology.Artigo de evento 0 Citação(ões) na Scopus Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs(2005-09-07) BELLODI, M.; MARTINO, J. A.Experimental and simulations analyzes were done in Graded-Channel (GC) SOI nMOSFETs in order to study the drain leakage current behavior in these devices when operating from room temperature (300K) up to 573K. It was noticed that drain leakage current depends strongly on the ratio between the length of the lowly doped region and the mask channel length. All discussions presented are based on experimental and numerical bidimensional simulations results.Artigo de evento 0 Citação(ões) na Scopus Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments(2005-09-07) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.The performance evaluation of conventional and graded-channel SOI MOSFETs operating as tunable resistors is performed from room temperature down to 90 K. The on-resistance, total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the on-resistance reduces with the temperature lowering and is smaller in any GC SOI than in conventional SOI due to the effective channel length reduction. The total harmonic distortion is weakly temperature dependent and decreases in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion is strongly temperature influenced, increasing 15 dB at 90 K with respect to room temperature operation. Conventional and GC SOI have similar third order harmonic distortion in all studied temperatures.