Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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11 resultados
Resultados da Pesquisa
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
- Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors' Mobility Variation Induced by Substrate Bias(2022) BERMAMASCHI, F. E.; RIBEIRO, T. A.; PAZ, B. C.; Michelly De Souza; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 1963-2012 IEEE.This work investigates the carrier mobility variation in Ω-gate silicon-on-insulator (SOI) nanowire MOS transistors induced by substrate (or back) biasing. The analysis is carried out through experimental measurements and 3-D TCAD simulation, performed in n-type devices with variable fin width. Mobility enhancement is observed for lower back bias levels, due to the initial conduction through the Si-BOX interface, which presents higher mobility, prior to the activation of the front channel. As back bias is increased, however, the strong substrate-induced electric field in the back channel (BC) is responsible for worsening scattering mechanisms in the BC, such as surface roughness and acoustic phonon scattering, inducing mobility degradation. The effect is amplified as the fin width increases. For short-channel devices, the use of back bias was more beneficial for mobility due to a stronger mobility enhancement and lower mobility degradation.
- Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures(2022-07-04) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K and 580 K. The study is conducted using experimental data, corroborated with 3D TCAD simulations. It is demonstrated that the GIDL current normalized by the total fin width is larger in nanosheet MOSFET than for the nanowire at high temperatures. Additionally, the nanosheet device presents a larger variation of the normalized GIDL current with the temperature than the nanowire one.
- On the compact modelling of Si nanowire and Si nanosheet MOSFETs(2022) CERDEIRA, A.; ESTRADA, M.; Marcelo Antonio PavanelloIn this paper, three-dimensional technology computer aided design simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in nanowire and nanosheet structures, are practically same. This characteristic makes it possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend of the application of the symmetric doped double-gate model (SDDGM) model to nanowires and nanosheets metal-oxide-semiconductor field effect transistors, with no need to include new parameters. The model SDDGM is validated for this application using several measured and simulated structures of nanowires and nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in the SmartSPICE circuit simulator.
- Analog, RF and nonlinear behaviors of submicron graded channel partially depleted SOI MOSFETs(2009-09-18) EMAM, M.; Marcelo Antonio Pavanello; DANNEVILLE, F.; VANHOENACKER-JANVIER, D.; RASKIN, J.-P.The DC, analog and RF behaviors as well as the nonlinear characteristics are shown for the first time for submicron graded channel partially depleted SOl MOSFETs. Previously reported advantages of long graded channel devices are extended for downscaled submicron graded channel devices presented in this work. These advantages cover all aspects of operation, being DC, analog, RF and nonlinear performances, which are investigated in comparison with classical MOS devices. These results are confirmed through robust measurements and accurate characterization techniques supported by well established extraction methods, especially for RF and nonlinear regimes of operation. ©2009 IEEE.
- Simulation of OTA's with double-gate graded-channel MOSFETS using the symmetric doped double-gate model(2010-01-05) CENTRERAS, E.; CERDEIRA, A.; Marcelo Antonio PavanelloIn this paper Operational Transconductance Amplifiers (OTA's) were simulated in SPICE, using the Symmetric Doped Double-Gate Model which includes the capacitances of Double-Gate (DG) transistors. In this work, all the transistors have been simulated using just one model for lightly doped transistor (TLD) and high doped transistor (THd) N-channel devices and P-channel devices. These OTA's show an improvement in the high open-loop voltage gain which is related mainly to the reduction of the drain output conductance which give higher Early voltages for DG GC transistors. ©The Electrochemical Society.
- Impact of substrate rotation and temperature on the mobility and series resistance of triple-gate SOI nMOSFETs(2011-09-02) Michely De Souza; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio PavanelloIn this work a comparative experimental analysis of the electron mobility and parasitic source-drain series resistance of triple-gate n-channel MOSFETs as a function of the temperature is carried out. Devices with different fin widths fabricated on standard non-rotated and 45° rotated SOI substrates were analyzed for temperatures ranging from 250 K to 400 K. It is shown that the use of rotated substrate does not affect the subthreshold slope or the threshold voltage variation with temperature of these devices. On the other hand, the change in the conduction plane not only improves the mobility, but also promotes a rise of its variation with temperature. Although the fin width reduction may cause an increase of the series resistance, the increased mobility of rotated devices is responsible for the series resistance roll-off and this reduction becomes larger as the fin is narrowed. © The Electrochemical Society.
- Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations(2012-03/17) MARINIELLO, G.; Rodrido Doria; Michelly De Souza; Marcelo Antonio Pavanello; TREVISOLI, R. D. G.Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D), fin width (W fin) and fin height (H fin). © 2012 IEEE.
- Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs(2012-10-04) Michelly De Souza; KILCHTYSKA, V.; FLANDRE, D.; Marcelo Antonio PavanelloFully Depleted (FD) SOI technology is well known to provide improved analog performance of CMOS transistors [1, 2]. However, FD SOI transistors may suffer from parasitic bipolar effects (PBE) that cause the degradation of the output conductance [3]. The use of cascode transistors with common gate (making a self-cascode-SC topology) has been shown to reduce the output conductance of MOSFETs, while keeping some advantages of long-channel transistors [4]. Fig. 1 represents the self-cascode transistor, composed by transistors MS and MD, with channel lengths LS and LD, and threshold voltages VT, S and VT, D, respectively (with VT, S = VT, D in the symmetric SC-S-SC). Recent works [5, 6] showed that the use of different threshold voltages (VT) for MS and MD (so-called asymmetric self-cascode-A-SC) is able to further enhance the analog properties of SC n-and pMOS transistors, in comparison to the S-SC, at room temperature (RT). In this paper the enhanced analog performance of asymmetric SC structure is experimentally demonstrated at deep cryogenic environments emphasizing its capability to minimize (or even suppress) PBE in FD SOI n-and p-type MOSFETs at liquid helium temperature (LHT), where this effect is more pronounced [7]. © 2012 IEEE.
- A New Method for Series Resistance Extraction of Nanometer MOSFETs(2017-07-05) TREVISOLI, R.; Rodrido Doria; Michelly De Souza; BARRAUD, S.; VINET, M.; CASSE, M.; REIMBOLD, G.; FAYNOT, O.; GHIBAUDO, G.; Marcelo Antonio PavanelloThis paper presents a new method for the series resistance extraction in ultimate MOSFETs using a single drain current versus gate voltage characteristic curve. The method is based on the Y-function curve, such that the series resistance is obtained through the curve of the total resistance as a function of the inverse of the Y-function. It includes both first-and second-order mobility degradation factors. To validate the proposed method, numerical simulations have been performed for devices of different characteristics. Besides, the method applicability has been demonstrated for experimental silicon nanowires and FinFETs. Apart from that, devices with different channel lengths can be used to estimate the mobility degradation factor influence.