Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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18 resultados
Resultados da Pesquisa
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
- Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors' Mobility Variation Induced by Substrate Bias(2022) BERMAMASCHI, F. E.; RIBEIRO, T. A.; PAZ, B. C.; Michelly De Souza; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 1963-2012 IEEE.This work investigates the carrier mobility variation in Ω-gate silicon-on-insulator (SOI) nanowire MOS transistors induced by substrate (or back) biasing. The analysis is carried out through experimental measurements and 3-D TCAD simulation, performed in n-type devices with variable fin width. Mobility enhancement is observed for lower back bias levels, due to the initial conduction through the Si-BOX interface, which presents higher mobility, prior to the activation of the front channel. As back bias is increased, however, the strong substrate-induced electric field in the back channel (BC) is responsible for worsening scattering mechanisms in the BC, such as surface roughness and acoustic phonon scattering, inducing mobility degradation. The effect is amplified as the fin width increases. For short-channel devices, the use of back bias was more beneficial for mobility due to a stronger mobility enhancement and lower mobility degradation.
- High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs(2023-01-05) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Pavanello M. A.AuthorIn this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.
- Performance of SOI Ω-Gate Nanowires from Cryogenic to High Temperatures(2022-09-17) Marcelo Antonio Pavanello; Michelly De Souza© 2022, Brazilian Microelectronics Society. All rights reserved.—This review paper presents the electrical characteristics of Silicon-On-Insulator Ω-Gate nanowires in a wide range of temperatures. The operation in cryogenic and high-temperature environments will be experimentally explored. The influence of nanowire width and channel length will be dis-cussed. Nanowires with and without strain will be investigated from room temperature down to cryogenic ones, showing that strained nanowires improve carrier mobility in the whole temperature range. At high temperatures, it is demonstrated that nanowires can operate successfully up to 580 K, maintaining the ideal body factor. The effect of high temperatures on Gate-In-duced Drain Leakage will also be studied. The experimental re-sults in the whole temperature range confirm that SOI nan-owires are an excellent alternative for FinFET replacement in future technological nodes.
- Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs(2023-01-04) ALVES, C. R.; Michelly De Souza© 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.This work presents a comparative study of the transcapacitances of an asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs with different gate lengths. This analysis was done by means of two-dimensional numerical simulations. Simulated results show the influence of others transcapacitances on the gate-to-gate capacitance for the ASC SOI device and the GC SOI device.
- Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures(2022-07-04) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K and 580 K. The study is conducted using experimental data, corroborated with 3D TCAD simulations. It is demonstrated that the GIDL current normalized by the total fin width is larger in nanosheet MOSFET than for the nanowire at high temperatures. Additionally, the nanosheet device presents a larger variation of the normalized GIDL current with the temperature than the nanowire one.
- Comparative Analysis of Transcapacitances in Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs(2022-07-04) ALVES, C. R.; D'OLIVEIRA, L. M.; Michelly De Souza© 2022 IEEE.This work presents a comparative study of the transcapacitances of asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs, by means of two-dimensional numerical simulations. Simulated results show that the gate-to-drain capacitance is smaller for the ASC SOI device if compared to the GC SOI device, despite of the applied VDS.
- An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires(2022) Michelly De Souza; RODRIGUES, J. C.; MARINIELLO, G.; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.In this work, an experimental evaluation of the gate-induced drain leakage (GIDL) of vertically stacked SOI nanowire (NW) FETs is carried out, as a function of temperature for the first time. It is shown that at room temperature, NW width decrease improves gate coupling favoring longitudinal band-to-band-tunneling, which increases normalized GIDL current. The increase of GIDL current with fin narrowing becomes more pronounced with temperature reduction. The influence of fin width has been evaluated, showing that GIDL variation with temperature depends on the device geometry.
- Analysis of Variability in Transconductance and Mobility of Nanowire Transistors(2022-08-22) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2022 IEEE.This work presents a comparison between the variability in junctionless nanowire transistors and inversion-mode nanowire transistors, looking at the transconductance, low-field mobility, linear and quadratic mobility degradation coefficients. To extract these parameters, the Y-Function method has been used. The obtained results shows differences in mobility and transconductance matching coefficients, indicating that mobility influence is not the only source of transconductance variation.
- Variability Modeling in Triple-Gate Junctionless Nanowire Transistors(2022-01-05) TREVISOLI, R.; Marcelo Antonio Pavanello; Rodrigo Doria; CAPOVILLA, C.E.; BARRAUD, S.; Michelly De SouzaIEEEThis work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.