Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

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Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors
(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza
© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
A fully analytical continuous model for graded-channel SOI MOSFET for analog applications
(2004-09-11) Michelly De Souza; Marcelo Antonio Pavanello; INIGUEZ, B.; FLANDRE, D.
In this work an analytical model of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is proposed for analog applications. The model is based on a series association of two conventional SOI nMOSFETs each representing one part of the GC SOI nMOSFET channel. From this assumption, we propose a current model that considers the GC SOI MOSFET as a conventional SOI transistor, represented by one part of the channel only, in which the drain voltage is modulated by the remaining part. The proposed model has been verified through the comparison between its results and experimental measurements, presenting a good agreement. Some important characteristics for analog circuits, such as transconductance and Early voltage, are compared between the model results and experimental curves.
A charge-based continuous model for small-geometry graded-channel SOI MOSFET's
(2005-09-07) Michelly De Souza; Marcelo Antonio Pavanello
In this work a continuous model for analog simulation of short-channel Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET is presented. Effects of channel length modulation and velocity saturation have been included in the model formulation, which is based on the series combination of two conventional SOI nMOSFETs, each one representing one of the regions of GC SOI MOSFET channel and its characteristics. Experimental results and numerical bidimensional simulations are used to validate the model with excellent agreement in both cases.
Charge-based continuous explicit equations for the transconductance and output conductance of submicron graded-channel SOI mosfet's
(2006-09-01) Michelly De Souza; Marcelo Antonio Pavanello
This paper presents charge-based continuous explicit equations for the transconductance and output conductance of submicron Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. Short-channel effects like channel length modulation, velocity saturation and drain-induced barrier lowering have been considered in the proposed expressions. Experimental results were used to test the equations by comparing not only the transconductance and the output conductance, but also the Early voltage and the open-loop voltage gain, showing a good agreement as well as smooth transitions between the different regions of operation, validating the proposed equations. © 2006 The Electrochemical Society.
Study of matching properties of graded-channel SOI MOSFETs
(2008-01-05) Michelly De Souza; FLANDRE, D.; Marcelo Antonio Pavanello
In this paper an overall analysis on the matching properties of Graded-Channel (GC) SOI MOSFETs in comparison to conventional SOI transistors is performed. Experimental results show that GC devices present poorer matching behavior in comparison to conventional SOI counterpart for equal mask channel length, whereas for same effective channel length, almost the same matching behavior. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to validate the model-based analysis both in linear and saturation regions.
SOI PIN diodes for temperature sensing in harsh environment
(2009-09-13) RUE, B.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.
We study the use of lateral SOI PIN diodes as thermometers in a large range of temperature from 100 K to 575 K and under radiations. These diodes indeed show very linear voltage vs temperature characteristics when biased with a constant current and can be successfully used in an integrated temperature sensor. The diodes are implemented in three SOI technologies: UCL 2μm process, Xfab1μm and OKI 0.15μm industrial processes. The OKI diode characteristics after neutron irradiation are also discussed.
Thin-film lateral SOI pin diodes for thermal sensing reaching the cryogenic regime
(2010-09-01) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio Pavanello
This paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.
Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion
(2011-09-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C.-W.; FERAIN, I.; AKHAVAN, N. D.; YAN, R.; RAZAVI, P.; YU, R.; FRANTI, A.; COLINGE, J-P.
This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.
Temperature and silicon film thickness influence on the operation of lateral SOI PIN photodiodes for detection of short wavelengths
(2011-09-05) Michelly De Souza; BULTEEL, O.; FLANDRE, D.; Marcelo Antonio Pavanello
This work presents an analysis of the temperature influence on the performance of a lateral thin-film SOI PIN photodiodes when illuminated by low wavelengths, in the range of blue and ultra-violet (UV). Experimental measurements performed from 100K to 400K showed that the optical responsitivity of SOI PIN photodetectors is affected by temperature change, being reduced at low and moderately high temperatures. Two-dimensional numerical simulations showed the same trends as in the experimental results, and were used both to investigate the physical phenomena responsible for the observed behavior as a function of the temperature as well as to predict the influence of silicon film thickness downscaling on the photodetector performance.
Impact of the series resistance in the I-V characteristics of junctionless nanowire transistors and its dependence on the temperature
(2012-01-05) Rodrigo Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio Pavanello
The effect of the source/drain parasitic resistance (R S) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on R S has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.

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