Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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12 resultados
Resultados da Pesquisa
Artigo de evento 9 Citação(ões) na Scopus Early voltage behavior in circular gate SOI nMOSFET using 0.13 μm partially-depleted SOI CMOS technology(2006-09-01) Salvador Gimenez; FERREIRA, R. M. G.; Joao Antonio MartinoThis paper studies the Early voltage behavior in circular gate partially-depleted SOI nMOSFET. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Drain current comparisons with rectangular gate partially-depleted SOI nMOSFET are performed, regarding the same effective channel length and width. Experimental results and three-dimensional simulations are used to qualify the results. © 2006 The Electrochemical Society.- Applying the diamond layout style for FinFET(2012-12-02) NETO, E. D.; Salvador GimenezThe FinFET devices have been on focus in recent years due its elevated gate control capability over the channel region, what gives this technology a scalability advantage against others. The planar Diamond MOSFET layout, on the other hand, has also shown great results regarding its possible use on integrated circuits applications. In this paper, the concept of the Diamond layout style is extended to its three-dimensional version, the Diamond FinFET. 3D numerical simulations are performed in order to compare the possible advantages and disadvantages between this innovative layout style and its conventional counterpart, keeping the same gate area, geometric factor and bias conditions. It is shown that this new device inherits the qualities of its planar MOSFET version and it is proved that it can reduce significantly the die area of the analog and digital (mixed) low-power low-voltage integrated circuits due to its high capability as current driver. © The Electrochemical Society.
- Comparison between harmonic distortion in circular gate and conventional SOI NMOSFET using 0.13 μm partially-depleted SOI CMOS technology(2007-10-12) DANTAS, L. P.; Salvador GimenezHarmonic distortion or linearity is an important merit figure for low-power, low-voltage analog integrated circuit applications. This paper studies the Harmonic Distortion in Circular Gate SOI nMOSFET, using 0.13 μm partially-depleted SOI CMOS technology for analog applications. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Circular gate SOI nMOSFET harmonic distortion comparisons with conventional (rectangular gate) partially-depleted SOI nMOSFET are made, regarding the same effective channel length and width. This paper is based on experimental results. The Integral Function Method (IFM) is used to determine the total harmonic distortion (THD) and third order harmonic distortion (HD3) in order to perform this work. It is observed that circular gate devices present improved harmonic distortion as compared with rectangular gate SOI nMOSFETs, for the same effective channel length and width. © The Electrochemical Society.
- The wave SOI MOSFET: A new accuracy transistor layout to improve drain current and reduce die area for current drivers applications(2009-05-29) Salvador GimenezThis paper proposes a new transistor layout, called here simply as Wave, that can be used for any technology, to improve the current driver and enhanced layout packing with respect to Multifinger and Waffle structures, regarding the same geometric factor Discussions about this novel layout approach are performed regarding matching, avalanche and electro static discharge. To verify the benefits of the Wave structure, a comparison with a Multifinger and Waffle is carried out. Defining a figure-of-merit as integration factor [(W/L)/A], the Wave features a better efficiency than Multifinger and Waffle layouts, as 35.9 % and 28.1% respectively. The Wave approach allows a saving of 26.1 % and 21.8% in the power SOI MOSFET size as compared to Multifinger and Waffle layouts. ©The Electrochemical Society.
- Comparative experimental study between diamond and conventional MOSFET(2010-01-05) Salvador Gimenez; ALATI, D.M.The focus of this work is to perform the experimental comparative study between Diamond and the conventional MOSFET counterpart in order to verify the benefits observed by three dimensional numerical simulations, considering the same geometric factor, die area and bias conditions, as described in first publication of Diamond style layout. The devices were manufactured by using the commercial manufacture CMOS process from 0.35μm AMI (On-Semiconductor) that is available in MOSIS Educational Program (MEP). The experimental results prove that Diamond MOSFET presents a better performance than one found in equivalent conventional transistor, except in relation to the Early voltage, due the higher impact ionization in the drain region than one observed in the conventional counterpart. Therefore the Diamond layout style is an important alternative to improve the performance of the analog, current drivers and pass switches integrated circuits applications. ©The Electrochemical Society.
- X-ray radiation effects in the circular-gate transistors(2011-01-05) CIRNE, K. H.; Marcilei Aparecida Guazzelli; DE LIMA, J. A.; SEIXAS JUNIOR, L. E.; Salvador GimenezThis work performs two experimental comparative analyses of the x-ray radiation effects in the Conventional, Wave and Overlapping-Circular-Gate nMOSFETs. In the first experiment, the x-ray radiation influence is studied without biasing the devices during the irradiation process, considering two channel lengths and after they have been exposed up to a x-ray irradiation of 1.5 Grad and with a dose ratio of 22 Mrad/min. The second one performs an experimental comparative study of the x-ray radiation influence between the Conventional and Overlapping-Circular Gate nMOSFET for a channel length equal to 12 μm, when they are submitted to the x-ray irradiation of 60 Mrad and maintaining the same bias conditions (overdrive gate and drain voltages) during the irradiation process. In both studies, we observe that the Overlapping-Circular Gate layout style presents higher x-ray irradiation robustness than those found in the other transistors studied, due to the absence of the bird's beak in Overlapping-Circular Gate MOSFET. ©The Electrochemical Society.
- Experimental study of the OCTO SOI nMOSFET and its application in analog integrated circuits(2012-09-02) FINO, L. N. D. S.; RENAUX, C.; FLANDRE, D.; Salvador GimenezThis paper presents an experimental comparative study between the OCTO, Diamond and Conventional Silicon-On-Insulator nMOSFETs (OSM, DSM and CSM, respectively), considering the same bias condition for all devices. The first comparison between the OSM and the CSM counterpart considers the same gate area and the second between the OSM and DSM regards the same geometric factor, in order to verify the benefits of the octagonal gate geometry, that uses the longitudinal corner effect to increase the resultant longitudinal electric field along of the channel, to improve the device performance and consequently to enhance the performance of analog integrated circuits. These characteristics can be observed on the main analog parameters such as drain current in saturation region, maximum transconductance, transconductance by drain current, voltage gain, unity voltage gain frequency and Early voltage. © The Electrochemical Society.
- Experimental validation of the drain current analytical model of the fully depleted diamond SOI nMOSFETs by using paired t-test statistical evaluation(2012-09-02) PERUZZI, V. V.; RENAUX, C.; FLANDRE, D.; Salvador GimenezThe focus of this work is to validate the drain current analytical model of the Fully Depleted Diamond SOI nMOSFETs, by applying the paired t-test statistical evaluation with experimental data of the six different samples of integrated circuits containing different Diamond SOI MOSFETs and Conventional ones counterparts. Two parameters are considered in this work: maximum transconductance and saturation drain current. We observe that, for the most cases (worst case is around 85% of the repeatability for the saturation drain current), the Diamond drain current analytical model is capable to reproduce a similar statistical behavior than the one observed for the conventional SOI nMOSFET counterpart, considering the same bias conditions and SOI CMOS manufacturing process of the integrated circuits. © The Electrochemical Society.
- Experimental comparative study between the wave layout style and its conventional counterpart for implementation of analog integrated circuits(2012-09-02) NAVARENHO, S. R.; Salvador GimenezThis paper performs an experimental comparative study between the Wave layout style ("S" shape gate geometry) and the Conventional (rectangular gate geometry) counterpart in order to verify and quantify the benefits that Wave structure can bring to improve the performance of devices in analog circuit, specially in trasconductance the ratio of transconductance between drain current as a function of the ratio of the drain current normalized by the geometric factor and frequency response (voltage gain and unit voltage gain frequency). By working with Wave structure instead of conventional counterpart, it can improve the device performance in terms of drain current in the triode and saturation regions, consequently better results in the transconductance and unit voltage gain frequency gains. © The Electrochemical Society.
- Innovative layout styles to boost the MOSFET electrical performance(2014-01-05) Salvador GimenezThis paper describes how to potentiate the electrical performance of MOSFETs using non-conventional layout styles (rectangular gate geometry), without causing any extra burden to the current ICs manufacturing CMOS process. This layout approach is based on "drain-channel region-source interfaces engineering", which is capable to add new effects to the MOSFET structure that contributes to improve the analog and digital electrical parameters of MOSFETs. Besides that, some of these new structures can enhance the transistor robustness in harsh environment (high temperature and radiation). Furthermore, as a first insight into exploration of this layout approach was applied in Multi-Gate MOSFETs (FinFET) by three-dimensional simulations and the results are very promising. © 2014 The Electrochemical Society.