Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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12 resultados
Resultados da Pesquisa
- Study of the drain leakage current behavior in circular gate SOI nMOSFET using 0.13μm SOI CMOS technology at high temperatures(2007) ALMEIDA, L. M.; BELLODI, M.It is presented numerical tridimensional simulations results concerning to the evolution of the drain leakage current behavior in Circular Gate SOI nMOSFETs operating from room temperature up to 573K. The results show that the leakage current behavior depends strongly on the channel length. Also, it was observed that the leakage current density distribution is non uniform along the silicon film thickness and it depends on the channel length and changes as the temperature goes up. © The Electrochemical Society.
- Sidewall angle influence on the FinFET analog parameters(2007-09-06) Renato Giacomini; MARTINO, J. A.; Marcelo Antonio PavanelloThe width variations along the vertical direction, due to process limitations, that appear in some fabricated FinFETs lead to non-rectangular cross-sectional shapes. One of the most frequent shapes is the trapezoidal (inclined sidewalls). These geometry variations may cause some changes in the device electrical characteristics. This work analyses the influence of the sidewall inclination angle on analog parameters, such as voltage gain, transconductance, output conductance, threshold voltage and also on the corner effects, through 3-D numeric simulation. © The Electrochemical Society.
- Physical characterization and reliability aspects of MuGFETs(2007-09-06) CLAEYS, C.; SIMOEN, E.; RAFI, J. M.; Marcelo Antonio Pavanello; MARTINO, J. A.Multi-gate devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling to the 32 nm and below technology nodes. Worldwide much attention is given to FinFET and MuGFET device architectures. This paper reviews some physical characterization and reliability aspects of such devices. Attention is given to aspects such as transient floating body effects, their performance at both high and low temperatures, gate coupling effects and their low frequency noise behavior. In addition, their potential radiation hardness in view of space applications is outlined. © The Electrochemical Society.
- Influence of the N-type FinFET width on the zero temperature coefficient(2007-09-07) BELLODI, M.; MARTINO, J. A.; CAMILO, L. M.; SIMOEN, E.; CLAEYS, C.This paper presents the influence of the Fin width dimension on the Zero Temperature Coefficient (ZTC) behavior for devices operating at high temperatures (from room temperature up to 573K). Besides this, a simple analytical model is presented in order to describe the ZTC behavior as the temperature increases. Three-dimensional simulations are carried out and compared with experimental results to support the interpretation presented along this work. © The Electrochemical Society.
- Simple analytical model to study the ZTC bias point in FinFETs(2007-05-11) BELLODI, M.; CAMILLO, L. M.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.In this work we present a simple analytical model to study the Zero Temperature Coefficient (ZTC) bias point in FinFETs operating from room temperature up to 573 K. Three-dimensional simulations are carried out and compared with experimental results to qualify the results. © The Electrochemical Society.
- Analysis of matching in graded-channel SOI MOSFETs(2007-09-06) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents an analysis of mismatch in Graded-Channel (GC) SOI MOSFETs. Experimental results show that GC devices present poorer threshold voltage and drain current matching in comparison to conventional SOI counterpart. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to predict the matching behavior both in linear and saturation regions. © The Electrochemical Society.
- Non-vertical sidewall angle influence on triple-gate FinFETs corner effects(2007-05-11) Renato Giacomini; MARTINO J. A.Some fabricated FinFET devices present width variations along the vertical direction due to fabrication process limitations. These variations lead to non-rectangular cross-section shapes. One of the most frequent shapes is the trapezoidal (plane and inclined sidewalls). Another identified phenomenon in multiple-gate devices such as FinFETs is the corner effect, which occurs due to the overlapping of the influences of two gate planes near the device corners. This paper addresses the variation of the corner effect as a function of the sidewall inclination angle, through 3-D numeric simulation. A set of devices of several inclination angles and body doping levels were simulated. The corner effect depends on the inclination angle, specially for higher doping levels. © The Electrochemical Society.
- Application of double gate graded-channel SOI in MOSFET-C balanced structures(2007-05-11) Rodrigo Doria; Marcelo Antonio Pavanello; CERDEIRA, A.; RASKIN J. P.; FLANDRE, D.This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices when applied in 2-MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive. © The Electrochemical Society.
- Comparison between harmonic distortion in circular gate and conventional SOI NMOSFET using 0.13 μm partially-depleted SOI CMOS technology(2007-10-12) DANTAS, L. P.; Salvador GimenezHarmonic distortion or linearity is an important merit figure for low-power, low-voltage analog integrated circuit applications. This paper studies the Harmonic Distortion in Circular Gate SOI nMOSFET, using 0.13 μm partially-depleted SOI CMOS technology for analog applications. The drain/source asymmetric effects are considered in terms of drain current as a function of the gate and drain voltages. Circular gate SOI nMOSFET harmonic distortion comparisons with conventional (rectangular gate) partially-depleted SOI nMOSFET are made, regarding the same effective channel length and width. This paper is based on experimental results. The Integral Function Method (IFM) is used to determine the total harmonic distortion (THD) and third order harmonic distortion (HD3) in order to perform this work. It is observed that circular gate devices present improved harmonic distortion as compared with rectangular gate SOI nMOSFETs, for the same effective channel length and width. © The Electrochemical Society.
- Low temperature operation of undoped body triple-gate FinFETs from an analog perspective(2007-09-06) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; ROOYACKERS R.; COLLAERT, N.; CLAEYS, CThis paper studies the temperature reduction influence on some analog figures of merit of n-type triple-gate FinFETs with undoped body, using DC measurements. It is demonstrated that the temperature reduction improves the transconductance over drain current ratio in any operational region. On the other hand, the output conductance is degraded when the temperature is reduced. The combination of these effects shows that the intrinsic gain of a L=90 nm FinFET is degraded by 3 dB when the temperature reduces from 300 K down to 100 K. A comparison with planar single gate fully depleted SOI reveals that the temperature degradation of the output conductance in FinFETs is less temperature-dependent. © The Electrochemical Society.