Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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58 resultados
Resultados da Pesquisa
- Analysis of the scattering mechanisms in the accumulation layer of junctionless nanowire transistors at high temperature(2019-08-05) RIBEIRO, T. A.; Marcelo Antonio Pavanello© 2019 IEEE.This work studies the effects of high temperature on the scattering mechanisms of Junctionless Nanowire Transistors with several fin width from nanowire to quasi-planar devices. With the variation of the temperature it was possible to analyze the impact of the scattering mechanisms on the devices. For nanowire devices at room temperature a degradation of up to 19% was seen from the maximum mobility to the mobility at higher gate bias to around 15% at 500K, while quasi-planar devices show a degradation of around 12% for all temperatures. Further analysis shows that the impact of the surface roughness for nanowires increase the degradation of these devices, where a reduction of its degradation at higher temperature shows the phonon scattering as the main scattering mechanism.
- The roles of the electric field and the density of carriers in the improved output conductance of junctionless nanowire transistors(2011-01-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C. W.; FERAIN, I.; DEHDASHTI AKHAVAN, N.; YAN, R.; RAZAVI, P.; YU, R.; KRANTI, A.; COLINGE, J. P.This paper evaluates the roles of the electric field (E) and the density of carries (n) in the drain conductance of Junctionless Nanowire Transistors (JNTs). The behavior of E and n presented by JNTs with the variation of the gate and the drain voltages has been compared to the one presented by Inversion Mode (M) Trigate devices of similar dimensions. It has been shown that the lower drain output conductance exhibited by Junctionless transistors with respect to the IM ones is correlated not only to the differences in the mobility and its degradation but also to the electric field, the density of carries and the first order derivative of these variables with respect the drain voltage. ©The Electrochemical Society.
- Analytical model for the threshold voltage in junctionless nanowire transistors of different geometries(2011-09-02) TREVISOLI, R. D.; Rodrigo Doria; Marcelo Antonio PavanelloJunctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era. As these devices have a constant doping profile from source to drain, they have a great scalability without the need for rigorously controlled doping and activation techniques. These devices also present a flexible threshold voltage, which strongly depends on the device cross section. This work proposes an analytical model for JNTs. The model is derived from the solution of the Poisson equation with the appropriate boundary conditions. The quantum confinement for devices of reduced dimensions has also been accounted. The threshold voltage in cylindrical and trigate JNTs are analyzed. Tridimensional numerical simulations were performed to validate the model. ©The Electrochemical Society.
- Impact of the series resistance in the I-V characteristics of nMOS junctionless nanowire transistors(2011-09-02) Rodrigo Doria; TREVISOLI, D. T.; Marcelo Antonio PavanelloThe series resistance (Rs) of Junctionless Nanowire Transistors (JNTs) with different doping concentrations was extracted from 473 K down to 100 K. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices and the impact of the series resistance on the drain current of the devices was evaluated. The R S analysis was carried out through experimental results and devices tridimensional numerical simulations. According to the study, R S presents opposite behavior with the temperature variation in EVI triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, whereas a resistance decrease is obtained with the temperature lowering in IM devices. The parasitic resistance in JNTs affects the drain current in such a way that there may not be a Zero Temperature Coefficient (ZTC) operation point. © The Electrochemical Society.
- Analysis of the low-frequency noise of junctionless nanowire transistors operating in saturation(2011-10-06) Rodrigo Doria; TREVISOLI, R. D.; Michelly De Souza; COLINGE, J.P.; Marcelo Antonio PavanelloThis work presented the LF noise behavior of nMOS JNTs investigated by experimental results. It was shown that JNTs can present either 1/f or 1/f 2 noises, depending on their operation region and the frequency. 1/f noise has been associated to carrier number fluctuations whereas 1/f 2 can be related to defects in the depletion layer. The W mask reduction degrades S Id at higher V GT (∼ 1 V) and present negligible influence on S Id at lower V GT (∼ 0.2 V). © 2011 IEEE.
- Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors(2012-01-05) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; DAS, S.; FERAIN, I.; Marcelo Antonio PavanelloThis paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model. © 2012 IEEE.
- Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements(2012-09-02) MARINIELLO, G.; Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire transistors have been recently proposed as an alternative to overcome the short channel effect caused by the reduction of the transistors dimensions. These devices behave like a gated resistor due to the lack of the p-n junctions in the channel/ source and channel/drain regions. The influence of doping concentration, silicon width, silicon height and gate oxide thickness on the intrinsic gate capacitances are presented in this paper by using three-dimensional numerical simulations and experimental results of fabricated devices. Also the influence of the applied drain bias in the components of the intrinsic gate capacitances is addressed. © The Electrochemical Society.
- Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance(2012-09-02) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloThe self-cascode (SC) configuration consists in a series association of two transistors with tied gates usually applied to improve the analog performance of MOS devices. This paper compares the analog parameters of single Junctionless transistors with the ones presented by self-cascode associations composed by two Junctionless devices with identical or different fin widths (symmetric and asymmetric, respectively). The transconductance to the drain current ratio, the Early voltage (VEA) and the intrinsic voltage gain (AV) have been evaluated for both single devices and SC structures. It has been shown that the SC configurations, specially the asymmetric ones, present a strong reduction of the drain conductance (gD) with respect to single devices, resulting in an increase of VEA and AV, which can be higher than 30 dB depending on the bias conditions. © The Electrochemical Society.
- Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors(2012-09-02) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloJunctionless nanowire transistors have a constant doping profile from source to drain, providing a great scalability without the need of rigorously controlled doping gradients and activation techniques. Therefore, these devices are considered as promising for decananometer era. This work proposes an analytical model for the drain current in junctionless nanowire transistor (JNT) accounting for short channel effects and temperature dependence. Tridimensional numerical simulations of p-type devices have been performed to validate the model. Experimental data of n-type devices have also been used. © The Electrochemical Society.
- Drain current model for junctionless nanowire transistors(2012-03-17) TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results. © 2012 IEEE.