Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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15 resultados
Resultados da Pesquisa
- Comparative Analysis of Transcapacitances in Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs(2022-07-04) ALVES, C. R.; D'OLIVEIRA, L. M.; Michelly De Souza© 2022 IEEE.This work presents a comparative study of the transcapacitances of asymmetric self-cascode (A-SC) and graded-channel (GC) silicon-on-insulator (SOI) nMOSFETs, by means of two-dimensional numerical simulations. Simulated results show that the gate-to-drain capacitance is smaller for the ASC SOI device if compared to the GC SOI device, despite of the applied VDS.
- Graded-channel SOI nMOSFET model valid for harmonic distortion evaluation(2006-05-17) Michelly De Souza; Marcelo Antonio Pavanello; CERDEIRA, A.; FLANDRE, D.In this paper an evaluation of the harmonic distortion of graded-channel SOI nMOSFETs is performed. The analysis is carried out by comparing an analytical continuous model and experimental results. The total harmonic distortion, as well as the third and second order terms are used as figures of merit in this comparison. It is shown that GC SOI devices present better gain and linearity behavior than conventional devices and that these advantages are well described by the proposed analytical model. The results show that the proposed set of equations is able to describe the linearity behavior of GC devices, indicating its potential to be used in analog circuit simulation and design. © 2006 IEEE.
- Analog, RF and nonlinear behaviors of submicron graded channel partially depleted SOI MOSFETs(2009-09-18) EMAM, M.; Marcelo Antonio Pavanello; DANNEVILLE, F.; VANHOENACKER-JANVIER, D.; RASKIN, J.-P.The DC, analog and RF behaviors as well as the nonlinear characteristics are shown for the first time for submicron graded channel partially depleted SOl MOSFETs. Previously reported advantages of long graded channel devices are extended for downscaled submicron graded channel devices presented in this work. These advantages cover all aspects of operation, being DC, analog, RF and nonlinear performances, which are investigated in comparison with classical MOS devices. These results are confirmed through robust measurements and accurate characterization techniques supported by well established extraction methods, especially for RF and nonlinear regimes of operation. ©2009 IEEE.
- Monte Carlo simulation of graded-channel fully depleted SOI nMOSFETs(2011-02-11) MARTIN M. J.; RENGEL R.; GALEOTE J. M.; Michelly De Souza; Marcelo Antonio PavanelloIn this paper a Monte Carlo investigation of Graded Channel (GC) Silicon-On-Insulator MOSFETs is presented. The influence of the length of the lightly-doped region of the channel (LLD) on the microscopic transport properties is exhaustively analyzed. Result show that increasing LLD provides an enhancement of the device performance in terms of drain current and transconductance. However, for LLD values larger than half of the channel the benefits are minimized from a microscopic point of view due to the increasing tendency of the device to behave as a lightly doped conventional transistor. This suggests the existence of an optimum L LD value to fully benefit from the improvements provided by GC doping techniques. © 2011 IEEE.
- Liquid helium temperature operation of graded-channel SOI nMOSFETs(2012-09-02) Michelly De Souza; KILCHYTSHA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThis work reports, for the first time, the operation of Graded-Channel SOI nMOSFETs at liquid helium temperature. As expected, for all measured devices it has been observed that at 4.2K the transconductance increases with respect to room temperature as a consequence of the mobility rise. On the opposite hand, all the studied devices demonstrated a degradation of the output conductance with temperature reduction. However, this degradation is attenuated below 90K. As a consequence, an increase of the Early voltage and of the intrinsic voltage gain were obtained, in contrast to the data reported in the literature, for devices operating down to 100K. It is demonstrated that GC SOI presented larger Early voltage increase at 4.2K than at room temperature. The rise of the voltage gain promoted by GC architecture has shown to be constant with temperature down to 4.2K. © The Electrochemical Society.
- Low frequency noise in submicron Graded-Channel SOI MOSFETs(2013-09-06) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThe origin of the low-frequency noise in submicron fully depleted Graded-Channel (GC) SOI MOSFET is investigated in terms of the channel length comparing two different technologies, OKI semiconductors and UCL. © 2013 IEEE.
- Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors(2014-01-20) ASSALTI, R.; Marcelo Antonio Pavanello; Michelly DE Souza; FLANDRE, D.This paper aims at analyzing, through two-dimensional numerical simulations and experimental results, the influence of technological parameters downscaling on the analog performance of Graded-Channel FD SOI nMOSFET transistors. Front gate oxide and silicon film thicknesses, channel doping concentration, total channel and lightly doped region lengths have been varied to target the highest intrinsic voltage gain.
- Field effect transistors: From mosfet to Tunnel-Fet analog performance perspective(2014-10-31) MARTINO, J. A.; AGOPIAN, P. G. D.; SIMOEN, E.; CLAEYS, C.© 2014 IEEE.This paper will discuss the analog behavior of the main insulated gate field effect transistor (FET) roadmap, like Silicon-On-Insulator (SOI) MOSFET, Graded-Channel (GC) SOI MOSFET, triple-gate SOI FinFET and Tunnel-FET (TFET) devices. The main analog Figures of Merit (FoM) like transconductance over drain current ratio, Early voltage, intrinsic voltage gain and unit gain frequency will be analyzed.
- Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias(2014-10-29) ASSALTI, R.; Marcelo Antonio Pavanello; FLANDRE, D.; Michelly De SouzaThis work assesses the analog performance of Graded-Channel FD SOI nMOSFET transistors regarding the dependence of gate voltage overdrive over the length of lightly doped region which maximizes the intrinsic voltage gain, unit gain frequency and breakdown voltage. It is shown that the optimum length of lightly doped region depends on the target application of GC devices.
- Asymmetric Self-Cascode versus Graded-Channel SOI nMOSFETs for analog applications(2015-10-13) ASSALTI, R.; Marcelo Antonio Pavanello; FLANDRE, D.; Michelly De SouzaThis paper compares the performance of Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs, both proposed to improve the analog performance of fully depleted SOI nMOSFETs. The differences at device level are evaluated and the impact of their application in basic analog circuits, i.e. common-source amplifier, source-follower and common-source current mirror are explored through experimental results.