Engenharia Elétrica

URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21

Navegar

Resultados da Pesquisa

Agora exibindo 1 - 10 de 29

Study of circular gate SOI nMOSFET devices at high temperatures
(2008-05-12) ALMEIDA, L. M.; BELLODI, M.
The aim of this work is to evaluate the drain leakage current behavior in a Circular Gate (CG) SOI nMOSFET fabricated in 0.13 μm SOI CMOS technology. This technology is analyzed operating since room temperature up to 300°C, where the channel length and the geometrical drain bias terminal influence are analyzed in the drain leakage current behavior, when the devices are operating at high temperatures, through 3D numerical simulations. Since the CG SOI nMOSFET is not a symmetrical structure, it is possible to have two different configurations as following: the one which structure is configured with external drain and another one, with internal drain. Analyzing the drain leakage current behavior as a function of channel length at high temperatures, it is possible to observe that for the same channel length, as the temperature increases, it becomes higher and it increases as the channel length reduces. On the other hand, when the devices are operating with external drain, the drain leakage current becomes lower as compared to the internal drain, for both devices operating at same conditions. The results show that the drain leakage current depends strongly on the channel length and its density distribution is non uniform along the silicon film thickness. Besides it, also was observed that the drain leakage current depends on drain terminal configuration. Then, in order to understand the drain configuration influence in the drain leakage current behavior at high temperatures, the electric field was analyzed into the silicon film.
Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures
(2022-07-04) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello
© 2022 IEEE.This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K and 580 K. The study is conducted using experimental data, corroborated with 3D TCAD simulations. It is demonstrated that the GIDL current normalized by the total fin width is larger in nanosheet MOSFET than for the nanowire at high temperatures. Additionally, the nanosheet device presents a larger variation of the normalized GIDL current with the temperature than the nanowire one.
Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors
(2013-09-06) DE SOUZA, M.; FLANDRE. D.; Marcelo Antonio Pavanello
This paper presents an experimental analysis of channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors. It is shown that the increase of the drain current and transconductance is more pronounced with the reduction of the length of the transistor close to the source (L1), and, differently from the symmetric self-cascode, suffers little influence of the length close to the drain (L2). On the contrary, the output conductance of symmetric and asymmetric threshold voltage structures is benefited by the increase of L 2 and L1, although the asymmetric structure may offer a reduction of up to one order of magnitude in comparison to the symmetric one. It results in larger intrinsic voltage drain for asymmetric devices. This increase has shown to reach more than 20 dB for similar dimensions, or allow for dimension reduction without intrinsic gain degradation. © 2013 IEEE.
Cross-coupling effects in common-source current mirrors composed by UTBB transistors
(2022) JOSÉ DA COSTA, F.; TREVISOLI, R.; Rodrigo Doria
© 2022 Elsevier LtdThis work performs an analysis of the cross-coupling effects influence on the performance of current mirrors composed by advanced UTBB SOI MOSFETs through 3D numerical simulations validated to experimental data of single devices. It is shown the presence of a capacitive coupling acting in the system, which can be demonstrated through the threshold voltage reduction at small distances between devices. Additionally, the temperature rise in the system due to the thermal coupling provokes a decrease in the input current as the devices become closer to each other. This is responsible for an increase of 3 % on ID2/ID1 ratio when the devices are biased at the same time and when the distance between them is lowered to 100 nm.
Analysis of matching in graded-channel SOI MOSFETs
(2007-09-06) Michelly De Souza; FLANDRE, D.; Marcelo Antonio Pavanello
This paper presents an analysis of mismatch in Graded-Channel (GC) SOI MOSFETs. Experimental results show that GC devices present poorer threshold voltage and drain current matching in comparison to conventional SOI counterpart. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to predict the matching behavior both in linear and saturation regions. © The Electrochemical Society.
Impact of graded-channel SOI MOSFET application on the performance of Cascode and Wilson current mirrors
(2007-09-06) FLANDRE, D.; Marcelo Antonio Pavanello
This work shows the impact of the use of graded-channel SOI MOSFETs (GC) in Wilson and Cascode current mirrors. The study was made through bi-dimensional simulations and experimental measurements, focusing on the mirroring precision, the output swing voltage (VOS) and output resistance of each architecture comparing with the conventional SOI devices. It was observed that the devices of graded-channel (GC) presented some improvement in the mirroring precision and a significant increase in the output resistance and output swing in all the architectures studied if compared to standard fully depleted SOI MOSEET. the setting time of GC current mirrors has been Also studied and has demonstrated improvements in relation to conventional SOI devices. © The Electrochemical Society.
Temperature influences on FinFETs with undoped body
(2007-05-11) Marcelo Antonio Pavanello; MARTINO J. A.; SIMOEN, E.; ROOYACKERS, R.; COLLAERT, N.; CLAEYS, C.
This work presents a study, based on DC measurements, of the temperature influence on the performance of nMOS triple-gate FinFETs with high-κdielectrics, TiN gate material and an undoped body. FinFETs show smaller threshold voltage variations with temperature than planar fully-depleted SOI MOSFETs. The subthreshold slope reduced with the temperature and approached the ideal value at lower temperatures In the temperature range under study the mobility increases linearly as the temperature is reduced and the dominating mobility degradation factor is phonon scattering. The DIBL has been evaluated and no temperature dependence has been found. Finally, the series resistance has been also extracted and demonstrates a reduction as the temperature is reduced due to the mobility improvement. © The Electrochemical Society.
The wave SOI MOSFET: A new accuracy transistor layout to improve drain current and reduce die area for current drivers applications
(2009-05-29) Salvador Gimenez
This paper proposes a new transistor layout, called here simply as Wave, that can be used for any technology, to improve the current driver and enhanced layout packing with respect to Multifinger and Waffle structures, regarding the same geometric factor Discussions about this novel layout approach are performed regarding matching, avalanche and electro static discharge. To verify the benefits of the Wave structure, a comparison with a Multifinger and Waffle is carried out. Defining a figure-of-merit as integration factor [(W/L)/A], the Wave features a better efficiency than Multifinger and Waffle layouts, as 35.9 % and 28.1% respectively. The Wave approach allows a saving of 26.1 % and 21.8% in the power SOI MOSFET size as compared to Multifinger and Waffle layouts. ©The Electrochemical Society.
Analysis of the low-frequency noise in graded-channel and standard SOI nMOSFET
(2010-01-05) DA SILVA, E. L. R.; MIGUEZ, M.; Michelly De Souza; ARNAUD, A.; Marcelo Antonio Pavanello
In this paper a comparison between the low-frequency noise in graded-channel SOI nMOSFETs (GC SOI MOSFET) and standard fully depleted (FD) SOI nMOSFETs will be presented. The evolution of noise with bias and frequency, mainly in the GC SOI MOSFETs, will be demonstrated. Numerical bidimensional simulations are used to reproduce the same tendencies observed experimentally in order to allow for a physical insight on the noise in GC SOI transistors. ©The Electrochemical Society.
An analytical model for the non-linearity of triple gate SOI MOSFETs
(2011-01-05) Rodrigo Doria; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.; Marcelo Antonio Pavanello
This work proposes a physically-based analytical model for the non-linearity of Triple-Gate MOSFETs. The model describes the second order harmonic distortion (HD2), usually the major non-linearity source, as a function of the device dimensions, the series resistance, the low field mobility and the mobility degradation factor (θ). The model was applied to transistors of different channel lengths and fin widths and allowed to conclude that θ is the parameter which most contributes for the increase of HD2. The model was validated for both unstrained and strained FinFETs. ©The Electrochemical Society.

Engenharia Elétrica

Navegar

Filtros

Configurações

Ordenar por

Resultados por página

Resultados da Pesquisa