Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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20 resultados
Resultados da Pesquisa
- Harmonic distortion in symmetric and asymmetric self-cascodes of UTBB FD SOI planar MOSFETs(2019-08-05) D'OLIVEIRA, L. M.; KILCHYTSKA, V.; FLANDRE, D.; Michelly De Souza© 2019 IEEE.This paper presents an analysis of the harmonic distortion extracted from simulated results of symmetric and asymmetric self-cascode devices (S-SC and A-SC, respectively) composed by ultra-thin body and BOX fully depleted silicon-on-insulator planar MOSFETs 28 nm technological node. The results show that the A-SC effectively increases the operating drain current range for lower distortion. Comparisons with the literature show that the A-SC structures are a promising option for enhancing the circuit design flexibility for advanced MOSFETs.
- Ultra-Low-Power Diodes Composed by SOI UTBB Transistors(2022-07-04) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to present an analysis of the performance of Ultra-Thin-Body and Buried Oxide transistors working as Ultra-Low-Power diodes. The implementation of different ground planes and substrate biases are analyzed. It is shown a reduced leakage current and increased ratio between the on and off-state currents for the Ultra-Low-Power diode with the N-substrate biased at -2V. However, this condition results in increased threshold voltage. The ground planes do not provoke a significant change in the leakage current, but a noticeable variation can be observed in the ratio between the on and off-state currents due to the higher threshold voltage in relation to the system without ground plane.
- Standard MOS Diodes Composed by SOI UTBB Transistors(2022-08-05) COSTA, F. J.; TREVISOLI, R.; CAPOVILLA, C. E.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to present an analysis of the performance of UTBB SOI transistors working as standard diodes, where the implementation of ground planes and substrate bias are analyzed. It is shown a reduced leakage current and increased ratio between the on and off-state currents with the substrate bias at -2 V and with a P-type GP implemented. However, both conditions result in increased threshold voltage.
- SOI UTBB Capacitive Cross-Coupling Effects in Ultimate Technological Nodes(2022-03-01) COSTA, F. J.; TREVISOLI, R.; Rodrigo Doria© 2022 IEEE.The main objective of this work is to carry out an analysis of the effects of cross-coupling in a system composed of SOI UTBB MOSFETs in ultimate integration nodes through numerical simulations, validated with experimental data from literature. In this analysis, it could be observed that two devices located on the channel length direction provoke a reduced cross-coupling on each other. For devices located at distances below 50 nm, a capacitive parasitic coupling between the devices can be observed along with the thermal coupling effect.
- Analysis and modelling of temperature effect on DIBL in UTBB FD SOI MOSFETs(2016-03-23) PEREIRA, A. S. N.; DE STREEL, G.; PLANES, N.; HAOND, M.; Renato Giacomini; FLANDRE, D.; KILCHYSKA, V.© 2016 IEEE.The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150°C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrarily to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs.Temperature prediction. Although being the closest to experiments, Fasarakis' model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ULV (ultra-low-voltage) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model showed very good agreement with experimental data, with high gain in precision for the gate lengths under test.
- Cross-coupling effects in common-source current mirrors composed by UTBB transistors(2022) JOSÉ DA COSTA, F.; TREVISOLI, R.; Rodrigo Doria© 2022 Elsevier LtdThis work performs an analysis of the cross-coupling effects influence on the performance of current mirrors composed by advanced UTBB SOI MOSFETs through 3D numerical simulations validated to experimental data of single devices. It is shown the presence of a capacitive coupling acting in the system, which can be demonstrated through the threshold voltage reduction at small distances between devices. Additionally, the temperature rise in the system due to the thermal coupling provokes a decrease in the input current as the devices become closer to each other. This is responsible for an increase of 3 % on ID2/ID1 ratio when the devices are biased at the same time and when the distance between them is lowered to 100 nm.
- Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures(2015-10-13) Rodrido Doria; FLANDRE, D.; TREVISOLLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThis paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
- Analysis of the substrate bias effect on the thermal properties of SOI UTBB transistors(2017-08-28) COSTA, F. J.; Marcelo Antonio Pavanello; TREVISOLI, R.; Rodrigo DoriaThis work presents an analysis of the thermal resistance of Ultra-Thin Body and Buried Oxide (UTBB) SOI (Silicon-on-Insulator) MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) under a selected set of back gate biases (Vsub), with and without considering the effect of the ground plane. It has been shown that the thermal resistance increases as the substrate bias is reduced. For negative Vsub, a thicker depletion depth is induced by the back gate, confining the overall current closer to the front gate and increasing its density. A thermal resistance reduction of about 8-9% can be obtained by simply increasing the back bias from -2V up to 2 V.
- Design benefits of self-cascode configuration for analog applications in 28 FDSOI(2018-03-21) D'OLIVEIRA, L.; DE SOUZA, M.; KILCHYTSKA, V.;FLANDRE. D.; Michelly De Souza; KILCHYTSKA, V.; FLANDRE. D.© 2018 IEEE.This paper showcases SPICE simulated results of single transistors and self-cascode (SC) associations of UTBB transistors from 28FDSOI technology by ST-Microelectronics with a focus on analog integrated circuit design. This comparison demonstrates significant improvement of the voltage gain for the SC association without compromising the transconductance, especially when featuring asymmetric threshold voltages (Asymmetric Self-Cascode - A-SC).
- Analysis of the output conductance degradation with the substrate bias in SOI UTB and UTBB transistors(2018-08-31) FERNO COSTA, J.; TREVISOLI, R.; Rodrigo Doria© 2018 IEEE.The goal of this work is to present the behavior of the output conductance in Ultra-Thin Body (UTB) and Ultra-Thin Body and Buried Oxide (UTBB) SOI {MOSFETs with the application of a selected set of back gate biases (VSUB) through AC simulations, in devices with and without considering the effect of the ground plane. It has been shown that the output conductance degradation due to self-heating and substrate effects increases as the substrate bias is reduced. The output conductance degradation by self-heating presents a reduction of about 52% and by substrate effects of 57% by simply increasing the back bias from-2V up to 2 V.