Artigos
URI permanente para esta coleçãohttps://repositorio.fei.edu.br/handle/FEI/798
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30 resultados
Resultados da Pesquisa
- Junctionless nanowire transistors effective channel length extraction through capacitance characteristics(2023-10-05) SILVA, E. M.; TREVISOLI, R.; Rodrigo Doria© 2023 Elsevier LtdThis work aims to extract the effective channel length (LEFF) of Junctionless Nanowire Transistors (JNT) through the maximum gate capacitance of the devices. The LEFF extraction has been done by extrapolating the maximum gate capacitance as a function of the devices’ channel length (LMASK) and has shown that LEFF is around 10–15 nm longer than LMASK for devices of different channel doping concentrations.
- Improved continuous model for short channel double-gate junctionless transistors(2014-09-05) PAZ, B. C.; AVILA, F.; CERDEIRA, A.; Marcelo Antonio Pavanello© 2014 IEEE.This work aims to present an evolution of a continuous model for short channel double-gate junctionless transistors, where the saturation velocity is included and model validation is spread to different doping concentrations, channel widths and shorter channel lengths. A long channel charge-based model for double-gate devices is used as a basis for the development of this model. To consider the short channel effects, the proposed model accounts for the influence of the drain bias in the channel potential, the reduction of the effective channel length in saturation regime and the saturation velocity effect for short channel transistors. Three dimensional numerical simulations will be used to validate the model.
- Performance of ultra-low-power SOI CMOS diodes operating at low temperatures(2011-01-05) Michelly De Souza; RUE, B.; FLANDRE, D.; Marcelo Antonio PavanelloIn this work the low temperature performance of ultra-low-power SOI CMOS diodes is presented. Experimental measurements performed in fabricated devices from 148K to 373K show that the temperature lowering can promote a significant leakage current reduction and increase of the forward current. Two-dimensional numerical simulations are used to extend the studied temperature range and analyze the doping concentration influence on the low temperature operation of these diodes. ©The Electrochemical Society.
- Impact of the series resistance in the I-V characteristics of nMOS junctionless nanowire transistors(2011-09-02) Rodrigo Doria; TREVISOLI, D. T.; Marcelo Antonio PavanelloThe series resistance (Rs) of Junctionless Nanowire Transistors (JNTs) with different doping concentrations was extracted from 473 K down to 100 K. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices and the impact of the series resistance on the drain current of the devices was evaluated. The R S analysis was carried out through experimental results and devices tridimensional numerical simulations. According to the study, R S presents opposite behavior with the temperature variation in EVI triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, whereas a resistance decrease is obtained with the temperature lowering in IM devices. The parasitic resistance in JNTs affects the drain current in such a way that there may not be a Zero Temperature Coefficient (ZTC) operation point. © The Electrochemical Society.
- Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements(2012-09-02) MARINIELLO, G.; Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio PavanelloJunctionless Nanowire transistors have been recently proposed as an alternative to overcome the short channel effect caused by the reduction of the transistors dimensions. These devices behave like a gated resistor due to the lack of the p-n junctions in the channel/ source and channel/drain regions. The influence of doping concentration, silicon width, silicon height and gate oxide thickness on the intrinsic gate capacitances are presented in this paper by using three-dimensional numerical simulations and experimental results of fabricated devices. Also the influence of the applied drain bias in the components of the intrinsic gate capacitances is addressed. © The Electrochemical Society.
- Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations(2012-03/17) MARINIELLO, G.; Rodrido Doria; Michelly De Souza; Marcelo Antonio Pavanello; TREVISOLI, R. D. G.Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (C gg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (N D), fin width (W fin) and fin height (H fin). © 2012 IEEE.
- An analytical estimation model for the spreading resistance of Double-Gate FinFETs(2012-03-17) MALHEIRO, C. T.; PEREIRA, A. S. N.; Renato GiacominiThe FinFET spreading resistance is the component of the parasitic resistance of FinFETs caused by the curved shape of the current lines in drain and source regions, close to the junctions. This work proposes a very simple analytical model for the spreading resistance of Double-Gate FinFETs that is valid for any fin width from 16nm, without fitting parameters. The model output was compared to data extracted from numeric simulation and it showed accuracy better than 8% for the considered range of devices with three different doping concentrations. © 2012 IEEE.
- Analog behavior of submicron graded-Channel SOI MOSFETs varying the channel length, doping concentration and temperature(2013-05-16) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductors were used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature. © The Electrochemical Society.
- Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors(2014-10-29) Rodrido Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThis paper reports the behavior of the effective mobility of n- and p-type SOI Trigate Junctionless Nanowire Transistors with different doping concentrations and channel widths down to 20 nm-wide devices. It is shown that the mobility of extremely narrow devices can overcome the bulk silicon mobility independently of the device type. The increase in the maximum mobility observed in narrow devices seems to be more pronounced for heavier doped devices.
- Ultra-low-power diodes using junctionless nanowire transistors(2015-03-18) Michelly De Souza; Rodrido Doria; TREVISOLI, R.D.; Marcelo Antonio PavanelloIn this work, the performance of Ultra-Low-Power (ULP) Diodes implemented with Junctionless Nanowire Transistors (JNTs) is presented for the first time. Experimental data of ULP Diodes formed by Junctionless Nanowire CMOS Transistors show that nanowire width, length and doping concentration play an important role in the reverse current of the diodes, affecting the on-off current ratio.
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