Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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11 resultados
Resultados da Pesquisa
- Asymmetric self-cascode configuration to improve the analog performance of SOI nMOS transistors(2011-10-11) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this work an asymmetric self-cascode (SC) structure implemented in a 150nm technology have been studied as a function of the threshold voltage and length of both transistors in the structure, aiming to improve the analog characteristics of FD SOI transistors. Experimal results indicate that this structure provided improvement in comparison to single and symmetric (SC) transistors, and that it depends on the saturation voltage of both transistors. The effect of threshold voltage and length variation of both transistors have been analyzed through 2D numerical simulations. The obtained results showed that the analog characteristics of the A-SC is improved both by reducing V T,2 and increasing L 1 and/or L 2, although there would be a maximum M 2 length in which no significant g D reduction is observed. By properly choosing these parameters, a g D reduction of more than one order of magnitude can be achieved. The A-SC has shown to provide an intrinsic voltage gain improvement of more than 20dB in comparison to single devices with similar effective channel length. © 2011 IEEE.
- Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors(2012-03-17) Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode. © 2012 IEEE.
- Analog performance of submicron GC SOI MOSFETs(2012-03-17) NEMER J. P.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length. © 2012 IEEE.
- Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs(2012-10-04) Michelly De Souza; KILCHTYSKA, V.; FLANDRE, D.; Marcelo Antonio PavanelloFully Depleted (FD) SOI technology is well known to provide improved analog performance of CMOS transistors [1, 2]. However, FD SOI transistors may suffer from parasitic bipolar effects (PBE) that cause the degradation of the output conductance [3]. The use of cascode transistors with common gate (making a self-cascode-SC topology) has been shown to reduce the output conductance of MOSFETs, while keeping some advantages of long-channel transistors [4]. Fig. 1 represents the self-cascode transistor, composed by transistors MS and MD, with channel lengths LS and LD, and threshold voltages VT, S and VT, D, respectively (with VT, S = VT, D in the symmetric SC-S-SC). Recent works [5, 6] showed that the use of different threshold voltages (VT) for MS and MD (so-called asymmetric self-cascode-A-SC) is able to further enhance the analog properties of SC n-and pMOS transistors, in comparison to the S-SC, at room temperature (RT). In this paper the enhanced analog performance of asymmetric SC structure is experimentally demonstrated at deep cryogenic environments emphasizing its capability to minimize (or even suppress) PBE in FD SOI n-and p-type MOSFETs at liquid helium temperature (LHT), where this effect is more pronounced [7]. © 2012 IEEE.
- Analog behavior of submicron graded-Channel SOI MOSFETs varying the channel length, doping concentration and temperature(2013-05-16) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloIn this paper the analog performance of Graded-Channel (GC) SOI nMOSFETs with deep submicrometer channel length is presented. Experimental data of GC transistors fabricated in an industrial 150 nm fully-depleted SOI technology from OKI Semiconductors were used to adjust the two-dimensional numerical simulations, in order to analyze the devices analog behavior by extrapolating their physical parameters. The obtained results show that the larger intrinsic voltage gain improvement occurs when the length of the lightly doped region is approximately 100 nm regardless the total channel length, doping concentration and temperature. © The Electrochemical Society.
- Analog operation of junctionless nanowire transistors down to liquid helium temperature(2014-07-09) TREVISOLI, R.; Michelly De Souza; Rodrido Doria; KILCHYTSHA, V.; FLANDRE, D.; Marcelo Antonio PavanelloThe aim of this work is to analyze the analog operation of Junctionless Nanowire Transistors at temperatures down to liquid helium temperature. The analysis is performed in terms of the transconductance, open loop voltage gain and output conductance for experimental long channel devices. It is shown that the temperature reduction can affect significantly the analog performance of the devices. © 2014 IEEE.
- Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias(2014-10-29) ASSALTI, R.; Marcelo Antonio Pavanello; FLANDRE, D.; Michelly De SouzaThis work assesses the analog performance of Graded-Channel FD SOI nMOSFET transistors regarding the dependence of gate voltage overdrive over the length of lightly doped region which maximizes the intrinsic voltage gain, unit gain frequency and breakdown voltage. It is shown that the optimum length of lightly doped region depends on the target application of GC devices.
- Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures(2015-10-13) Rodrido Doria; FLANDRE, D.; TREVISOLLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThis paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
- Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias(2015-11-20) Rodrido Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.
- Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors(2017-10-10) Rodrido Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices.