Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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13 resultados
Resultados da Pesquisa
- Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors(2023-10-05) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSÉ, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2023 Elsevier LtdThis work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors.
- Analysis of Variability in Transconductance and Mobility of Nanowire Transistors(2022-08-22) SILVA, L. M. B. DA; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; VINET, M.; FAYNOT, O.; Michelly De Souza© 2022 IEEE.This work presents a comparison between the variability in junctionless nanowire transistors and inversion-mode nanowire transistors, looking at the transconductance, low-field mobility, linear and quadratic mobility degradation coefficients. To extract these parameters, the Y-Function method has been used. The obtained results shows differences in mobility and transconductance matching coefficients, indicating that mobility influence is not the only source of transconductance variation.
- Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures(2022-08-22) PRATES, R. R.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello© 2022 IEEE.This work aims to present the electrical properties of junctionless and inversion-mode nanowires MOSFETs in the temperature range from 300 K to 580 K. Devices with different fin widths are compared. The comparison is performed using experimental data looking for some of the fundamental electrical parameters of these transistors such as threshold voltage, inverse subthreshold slope, current, and carrier mobility over the temperature.
- Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors(2021-09-06) Michelly De Souza; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOR, O.; Marcelo Antonio PavanelloIn this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire n MOS transistors is presented. Die-to-die variability of threshold voltage and drain current is presented and compared to inversion mode nanowire with the same dimensions. Although the junctionless nanowires have shown larger threshold voltage matching coefficients than inversion mode devices, the variability obtained experimentally has shown to be smaller than predicted by some simulations reported in the literature. Also, it has been shown that as the channel length of junctionless nanowire transistors is reduced, the current variability becomes smaller than in inversion mode nanowires, at the same current level and dimensions.
- The roles of the electric field and the density of carriers in the improved output conductance of junctionless nanowire transistors(2011-01-05) Rodrigo Doria; Marcelo Antonio Pavanello; TREVISOLI, R. D.; Michelly De Souza; LEE, C. W.; FERAIN, I.; DEHDASHTI AKHAVAN, N.; YAN, R.; RAZAVI, P.; YU, R.; KRANTI, A.; COLINGE, J. P.This paper evaluates the roles of the electric field (E) and the density of carries (n) in the drain conductance of Junctionless Nanowire Transistors (JNTs). The behavior of E and n presented by JNTs with the variation of the gate and the drain voltages has been compared to the one presented by Inversion Mode (M) Trigate devices of similar dimensions. It has been shown that the lower drain output conductance exhibited by Junctionless transistors with respect to the IM ones is correlated not only to the differences in the mobility and its degradation but also to the electric field, the density of carries and the first order derivative of these variables with respect the drain voltage. ©The Electrochemical Society.
- Impact of the series resistance in the I-V characteristics of nMOS junctionless nanowire transistors(2011-09-02) Rodrigo Doria; TREVISOLI, D. T.; Marcelo Antonio PavanelloThe series resistance (Rs) of Junctionless Nanowire Transistors (JNTs) with different doping concentrations was extracted from 473 K down to 100 K. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices and the impact of the series resistance on the drain current of the devices was evaluated. The R S analysis was carried out through experimental results and devices tridimensional numerical simulations. According to the study, R S presents opposite behavior with the temperature variation in EVI triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, whereas a resistance decrease is obtained with the temperature lowering in IM devices. The parasitic resistance in JNTs affects the drain current in such a way that there may not be a Zero Temperature Coefficient (ZTC) operation point. © The Electrochemical Society.
- Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors(2012-10-04) Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; FERAIN, I.; DAS, S.; Marcelo Antonio PavanelloMulti-gate architecture has been considered as one of the most viable alternatives to MOS devices scaling below 22 nm nodes [1] due to its stronger robustness to the short channel effects with respect to planar architectures. In short channel devices, the control of the gate over the channel charges dramatically decreases making the use of planar devices extremely challenging. Despite providing an improved coupling between gates and channel, conventional inversion mode (IM) multi-gate structures such as Trigate and FinFETs present p-n junctions between source/drain and channel, which can become an important bottleneck for ultimate technologies in which the formation of ultra-sharp junctions is needed in order to avoid the source/drain dopants diffusion into the channel. A novel multi-gate architecture so-called Junctionless Nanowire Transistor (JNT) was recently developed to overcome this bottleneck [2-3]. The JNT consists of a silicon nanowire surrounded by gate stack and is different from multi-gate IM devices due to its doping profile which is heavy and constant between source, channel and drain without any dopant gradients. The longitudinal sections of both a pMOS and an nMOS JNT are shown in Fig. 1 where the p-type is doped with boron and the n-type ones with phosphorous. The silicon nanowire needs to have a square-section small enough to be fully depleted at low gate voltages, turning off the device. Above threshold, the current flows mainly due to bulk conduction [4]. Several papers have shown the potentiality of the JNT for technological nodes beyond 10 nm [2-6] since it provides better DIBL, subthreshold slope and analog properties than IM multi-gate transistors of similar dimensions [5,6]. Although the Low-Frequency Noise (LFN) of JNTs has been treated in different papers [7,8], only long devices have been evaluated up to now and in none of them the LFN of pMOS was addressed as proposed in the current paper. © 2012 IEEE.
- Temperature and back-gate bias influence on the operation of lateral SOI PIN photodiodes(2014-09-05) NOVO, C.; GIACOMINI, R. DORIA, R.; AFZALIAN, A.; FLANDRE. D.Temperature and back-gate bias influence on the operation of lateral SOI PIN photodiodes. 2014 29th Symposium on Microelectronics Technology and Devices: Chip in Aracaju, SBMicro 2014,; Renato Giacomini; Rodrigo Doria; AFZALIAN, A.; FLANDRE. D.© 2014 IEEE.This paper presents a study of back-gate bias and temperature influence on the operation of lateral SOI PIN photodiodes. Experimental results showed that the operation mode of the photodiodes is affected by back-gate bias, modifying the photogenerated current, which has a strong influence on the illuminated to dark ratio, as well as, on the quantum efficiency. At lower temperatures, the results showed that the quantum efficiency can be improved by biasing the device in inversion mode, while at higher temperatures, the accumulation mode showed a higher illuminated to dark ratio.
- Physical insights on the dynamic response of junctionless nanowire transistors(2016-11-02) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio PavanelloThe aim of this work is to present, for the first time, an analysis of the maximum oscillation frequency (fmax) presented by Junctionless Nanowire Transistors (JNTs) as well as its impact and the carriers transit time on the minimum switching time of these devices. It has been observed that despite presenting lower fmax than inversion mode devices, fmax of JNTs is benefited by its lower capacitances along a large interval in its operation range. Also, it has been shown that the transit time can significantly influence on the minimum switching time of long devices, since it can be larger than the minimum oscillation time, what does not occur in shorter JNTs.
- Experimental comparative analysis between junctionless and inversion mode nanowire transistors down to 10 nm-long channel lengths(2018-10-18) Rodrigo Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; VINET, M.; CASSE, M.; FAYNOT, O.This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.