Engenharia Elétrica
URI permanente desta comunidadehttps://repositorio.fei.edu.br/handle/FEI/21
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13 resultados
Resultados da Pesquisa
- Analysis of matching in graded-channel SOI MOSFETs(2007-09-06) Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThis paper presents an analysis of mismatch in Graded-Channel (GC) SOI MOSFETs. Experimental results show that GC devices present poorer threshold voltage and drain current matching in comparison to conventional SOI counterpart. The analytical model for the drain current of GC devices is used to investigate the reasons for this matching worsening. Two-dimensional numerical simulations are used to predict the matching behavior both in linear and saturation regions. © The Electrochemical Society.
- Impact of graded-channel SOI MOSFET application on the performance of Cascode and Wilson current mirrors(2007-09-06) FLANDRE, D.; Marcelo Antonio PavanelloThis work shows the impact of the use of graded-channel SOI MOSFETs (GC) in Wilson and Cascode current mirrors. The study was made through bi-dimensional simulations and experimental measurements, focusing on the mirroring precision, the output swing voltage (VOS) and output resistance of each architecture comparing with the conventional SOI devices. It was observed that the devices of graded-channel (GC) presented some improvement in the mirroring precision and a significant increase in the output resistance and output swing in all the architectures studied if compared to standard fully depleted SOI MOSEET. the setting time of GC current mirrors has been Also studied and has demonstrated improvements in relation to conventional SOI devices. © The Electrochemical Society.
- Analog performance of submicron GC SOI MOSFETs(2012-03-17) NEMER J. P.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length. © 2012 IEEE.
- Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs(2012-10-04) Michelly De Souza; KILCHTYSKA, V.; FLANDRE, D.; Marcelo Antonio PavanelloFully Depleted (FD) SOI technology is well known to provide improved analog performance of CMOS transistors [1, 2]. However, FD SOI transistors may suffer from parasitic bipolar effects (PBE) that cause the degradation of the output conductance [3]. The use of cascode transistors with common gate (making a self-cascode-SC topology) has been shown to reduce the output conductance of MOSFETs, while keeping some advantages of long-channel transistors [4]. Fig. 1 represents the self-cascode transistor, composed by transistors MS and MD, with channel lengths LS and LD, and threshold voltages VT, S and VT, D, respectively (with VT, S = VT, D in the symmetric SC-S-SC). Recent works [5, 6] showed that the use of different threshold voltages (VT) for MS and MD (so-called asymmetric self-cascode-A-SC) is able to further enhance the analog properties of SC n-and pMOS transistors, in comparison to the S-SC, at room temperature (RT). In this paper the enhanced analog performance of asymmetric SC structure is experimentally demonstrated at deep cryogenic environments emphasizing its capability to minimize (or even suppress) PBE in FD SOI n-and p-type MOSFETs at liquid helium temperature (LHT), where this effect is more pronounced [7]. © 2012 IEEE.
- Improving the X-ray radiation tolerance of the analog ICs by using OCTO layout style(2013-09-06) FINO, L. N. D. S.; Marcilei Aparecida Guazzelli; RENAUX, C.; FLANDRE, D.; Salvador GimenezThis paper investigates and compares experimentally the total ionizing dose (TID) effects in the main analog parameters of the fully depleted (FD) OCTO Silicon-On-Insulator (SOI)n-type Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) (OSM), that presents an octagonal gate geometry, versus its conventional (rectangular gate geometry) counterpart (CSM). The main analog parameters taken into account in this study are the drain current in saturation region (IDSsat), the maximum transconductance (gm-max), the transconductance (gm) over the drain current (IDS) ratio (gm/IDS), the unity voltage gain frequency (f T), intrinsic voltage gain (AV) and Early voltage (V EA). This work demonstrates that OCTO layout style achieved the same relative variation due the TID effects as the conventional for the main analog parameters, but keeping the higher electrical performance related to the LCE and PAMDLE effects. In addition the OSM had a higher tolerance in terms of g m-max, IDSsat and VEA relative variation and fT and AV performance in strong inversion regime. © 2013 IEEE.
- Low frequency noise in submicron Graded-Channel SOI MOSFETs(2013-09-06) NEMER, J. P.; Michelly De Souza; FLANDRE, D.; Marcelo Antonio PavanelloThe origin of the low-frequency noise in submicron fully depleted Graded-Channel (GC) SOI MOSFET is investigated in terms of the channel length comparing two different technologies, OKI semiconductors and UCL. © 2013 IEEE.
- Analysis of harmonic distortion of asymmetric self-cascode association of SOI nMOSFETs operating in saturation(2014-01-20) D'OLIVEIRA, L. M.; Rodrigo Doria; Marcelo Antonio Pavanello; Michelly De Souza; FLANDRE, D.This paper presents an experimental analysis of the harmonic distortion of asymmetric self-cascode (A-SC) association of SOI transistors. This goal is achieved by comparing the A-SC to the symmetric self-cascode (S-SC) configuration with different channel lengths. The non-linearity data have been obtained by applying the Integral Function Method to experimental measurements, for the evaluation of the total and third-order harmonic distortion. The results show that the asymmetric self-cascode provides lower total harmonic distortion than S-SC for all studied channel length associations. If a target distortion level is fixed, the A-SC enables an increase of input signal amplitude. On the other hand, smaller input signal amplitude and distortion are verified in the A-SC when fixing the output amplitude.
- Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias(2015-11-20) Rodrido Doria; TREVISOLI, R.; Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.
- Advantages of subthreshold operation of asymmetric self-cascode SOI transistors aiming at analog circuit applications(2015-11-20) Michelly De Souza; Marcelo Antonio Pavanello; FLANDRE, D.This paper presents the analog characteristics of asymmetric self-cascode SOI nMOSFETs biased in subthreshold region aiming at low power low voltage analog applications. It is shown for the first time that the advantages of this structure in comparison to single transistors and symmetric self-cascode is sustained below threshold and improves as device moves to subthreshold.
- Boosting the MOSFETs matching by using diamond layout style(2016-09-03) PERUZZI, V. V.; RENAUX, C.; FLANDRE, D.; Salvador Gimenez© 2016 IEEE.This paper performs an experimental comparative study of the Metal-Oxide-Semiconductor Silicon-On-Insulator (SOI) Field Effect Transistors (MOSFETs) matching, which are implemented with the hexagonal gate geometry (Diamond) and classical rectangular one. Some of the main analog parameters of 360 devices are investigated. The results demonstrate that the Diamond SOI MOSFETs with α angles equal to 53.1° and 90° are capable of boosting in more than 20% the devices matching in comparison to those observed in the typical rectangular SOI MOSFETs, regarding the same gate area and bias conditions. Therefore, the Diamond layout style is an alternative technique to reduce the MOSFETs' mismatching regarding the analog SOI CMOS ICs applications.