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Halo effects on 0.13 μm floating-body partially depleted SOI n-Mosfets in low temperature operation
(2003-10-12) MARTINO, J. A.; Marcelo Antonio Pavanello; SIMOEN, E.; CLAEYS, C.
This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation, Parameters such as the Drain Induced Barrier Lowering and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 - 300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature.
Operation of double gate graded-channel transistors at low temperatures
(2003-10-16) Marcelo Antonio Pavanello; MARTINO, J. A.; CHUNG, T. M.; KRANTI, A.; RASKIN, J. P.; FLANDRE, D.
This work studies the use of graded-channel profile on double gate SOI MOSEETs from room temperature down to 95 K with the aim of studying the analog performance. Two-dimensional simulations are performed to provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs. It is demonstrated that double gate graded-channel MOSFETs can provide extremely improved Early voltage, high transconductance and drive current in comparison to the conventional double gate fully depleted SOI MOSFETs with similar dimensions. A degradation in the Early voltage as the temperature decreases has been found but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150 K to 300 K due compensation provided by the transconductance to drain current ratio.
Stocks classification using fuzzy clustering
(2004-06-21) Renato Aguiar; SALES, R. M.; DE SOUSA, L. A.; IMONIANA, J. O.
The main objective of this paper is to investigate the application of a pattern recognition technique as a supporting tool for stock investment decision taking by the public companies in the Brazilian Stock Market. The technique, known as fuzzy clustering means is applied to a set of indexes extracted from the quarterly financial statements relating to the 4 th quarter of 1994 through the 2nd quarter of 2002 belonging to oil/petrochemical and textile companies. The technique separates a group of companies into two sets. Having a set with higher potential returns than the other. And besides that, the set of stocks of the companies produced a higher potential yields and an average financial returns closer to the Bovespa index.
Digital signal processing with MatLab and DSP Kits
(2004-08-04) MELO, M. A. A. DE; Fabrizio Leonardi; LA NEVE, A.
A methodology, based on progressive steps, has been developed, so that the students be prepared to design and implement typical industrial projects, such as digital filters, voice processing algorithms, and others, and also be able to correlate this knowledge with other disciplines. They start with an analog system, described by a differential equation, from which a generic discrete equation is generated. The projects are initially simulated with MatLab, and they are then implemented with DSP TMS320C31. The projects are always based on a fundamental equation of differences, representing a digital filter: this is very important for the study of digital processing concepts, such as system stability, system order, computational complexity, and so on. The simulation helps the students to understand a system digitalization process. The results obtained with the students in the course show the efficiency of this methodology. ©2004 IEEE.
Distributed DSP processing for multivariable state equations
(2004-08-04) Fabrizio Leonardi; MELO, M. A. A. DE; LA NEVE, A.
This work deals with the synthesis of a multivariable digital controller when its hardware must be decentralized. Thus, it can be used as a way to implement dynamic equations in state space for hardware with limited inputs and outputs. The method consists in breaking equations, while keeping the overall transfer matrix, resulting in a distributed implementation. The solution has a modular structure for an arbitrary number of inputs and outputs. It is shown a way to perform the synthesis by using the same dynamic matrix. As a consequence the computational demand could not be severely reduced when compared with a centralized controller. Nevertheless, the synthesis is actually distributed since each part is implemented with a smaller number of inputs and outputs. A multivariable controller of an inverted pendulum is used as an example. ©2004 IEEE.
An improved model for the triangular SOI misalignment test structure
(2004-09-07) Renato Giacomini; MARINO, J. A.
The triangular misalignment test structure is an arrangement of MOS transistors to calculate the poly and source/drain diffusion misalignment as a function of drain current differences. Although these structures have non-rectangular shapes, which may be detrimental for the design, the advantage of measuring currents instead of voltage differences make them very useful. This work presents a new analytic misalignment error model for thin-film, fully depleted SOI technology, using non rectangular devices. Three-dimensional numerical simulation is used as a reference for models comparison and verification. These simulation results show that the proposed analytical model presents an improved performance compared to those available in the literature.
Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures
(2004-09-11) SANTOS, C. D. G. DOS; Marcelo Antonio Pavanello; MARTINO, J. A.; FLANDRE, D.; RASKIN, J.-P.
This paper presents the behavior of Graded Channel SOI Gate-All-Around (GAA) nMOSFET at high temperatures in the range of 27°C to 300°C. Threshold voltage, subthreshold slope, maximum transconductance, zero temperature coefficient and Early voltage were investigated through three-dimensional simulations and electrical characterization. It was verified that when temperature increases, threshold voltage decreases, subthreshold slope increases and did not suffer any degradation with the LLD/L ratio increase. The maximum transconductance decreases when temperature increases, and increases for larger LLD/L ratios, and Early voltage decreases almost linearly with temperature increase. The results show the excellent behavior of GC SOI GAA nMOSFET at high temperatures compared to conventional SOI GAA devices.
A fully analytical continuous model for graded-channel SOI MOSFET for analog applications
(2004-09-11) Michelly De Souza; Marcelo Antonio Pavanello; INIGUEZ, B.; FLANDRE, D.
In this work an analytical model of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs is proposed for analog applications. The model is based on a series association of two conventional SOI nMOSFETs each representing one part of the GC SOI nMOSFET channel. From this assumption, we propose a current model that considers the GC SOI MOSFET as a conventional SOI transistor, represented by one part of the channel only, in which the drain voltage is modulated by the remaining part. The proposed model has been verified through the comparison between its results and experimental measurements, presenting a good agreement. Some important characteristics for analog circuits, such as transconductance and Early voltage, are compared between the model results and experimental curves.
Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures
(2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.
An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.
Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures
(2004-09-11) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
The use of partially depleted deep-submicrometer SOI nMOSFETs in mixed mode applications is discussed in terms of channel engineering and temperature of operation. It is shown that the halo implantation used to obtain better digital characteristics degrades the gain and the unity gain frequency in comparison to devices that are not subjected to this implantation.
Improved current mirror performance using graded-channel silicon-on-insulator devices in high temperature operation
(2004-09-11) FERREIRA, R. S.; Marcelo Antonio Pavanello
This work studies the output characteristics of analog current mirror using graded-channel in comparison to conventional Silicon-On-Insulator MOSFETs in high temperature operation. The output characteristics are discussed, based on simulation and experimental results. The Mirroring Precision, Output Swing and Output Resistance are extremely improved at high temperature thanks to the reduced output conductance in graded-channel transistors.
On-resistance and harmonic distortion in graded-channel SOI FD MOSFET
(2004-11-05) CERDEIRA, A.; ALEMAN, M. A.; Marcelo Antonio Pavanello; MARTINO, J. A.; VANCAILLIE, L.; FLANDRE, D.
In this paper we analyze the advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The study of the two major figures of merit in such applications, i.e. on-resistance and non-linear harmonic distortion, is supported by measurements on conventional and Graded-Channel (GC) fully depleted (FD) SOI MOSFETs. The quasi linear I-V characteristics of GC transistors demonstrate a decrease of the on-resistance as the length of the low doped region into the channel is augmented and an improvement of the third order harmonic distortion (HD3), when compared with conventional transistors. A full comparison method between conventional and GC SOI MOSFETs is presented considering HD3 evolution with on-resistance tuning under low voltage of operation, demonstrating the significant advantages of the asymmetrical long channel transistors. © 2004 IEEE.
Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs
(2005-05-20) Salvador Gimenez; Marcelo Antonio Pavanello; Joao Antonio Martino; FLANDRE, D.
This paper presents the performance of operational transconductance amplifiers (OTAs) fabricated with Graded-Channel (GC) SOI nMOSFETs at room temperature. Different design targets were taken in account such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with high voltage gain and high unit voltage gain frequency OTAs made with conventional SOI nMOSFETs are performed showing that the GC OTAs present larger open-loop voltage gain without degrading unit voltage gain frequency, the phase margin, and slew rate with a significant required die area reduction depending on used LLD/L ratio. Experimental results and SPICE simulations are used to validate the analysis.
The temperature mobility degradation influence on the ZTC of PD and FD SOI MOSFETs
(2005-05-20) CAMILO, L. M.; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
The Zero Temperature Coefficient (ZTC) is observed experimentally in partially and fully depleted SOI MOSFET fabricated in a 0.13μm SOI CMOS technology. A simple model to study the behavior of gate voltage at ZTC (V ZTC) is proposed. The influence of the temperature mobility degradation in VZTC: is analyzed for PD and FD devices. Experimental results show that the temperature mobility degradation is larger in FD than in PD devices which is responsible for the VZTC decrement observed in FD instead of the increment observed in PD when the temperature increase. A good agreement is found in spite of the simplification used for VZTC model as a function of temperature.
Analysis of deep submicrometer bulk and fully depleted SOI nmosfet analog operation at cryogenic temperatures
(2005-05-20) Marcelo Antonio Pavanello; Joao Antonio Martino; SIMOEN, E.; CLAEYS, C.
The increased demand for mixed mode digital-analog circuits is playing an important role nowadays. As the temperature of operation is decreased well-known improvements in the digital characteristics as reduction of the subthreshold slope and increased carrier mobility are obtained leading to better performance characteristics without scaling the dimensions. In this work, the impact of the temperature reduction on the analog characteristics of deep submicrometer bulk and fully depleted SOI nMOSFETs is compared. It is shown that the Early voltage does not vary appreciably with temperature and the intrinsic gain is substantially improved in bulk deep submicrometer transistors. On the other hand, deep submicrometer fully depleted SOI can operate at reduced bias current to bias the same load in base-band applications.
Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications
(2005-05-20) Marcelo Antonio Pavanello; CERDEIRA, A.; ALEMAN, M. A.; Joao Antonio Martino; VANCAILLE, L.; FLANDRE, D.
An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature down to 90 K. The total harmonic distortion as a function of the transconductance over drain current ratio has been adopted as figure of merit. It is shown that the total harmonic distortion increases as the input voltage rises and the temperature is lowered. The use of lateral channel engineering in graded-channel transistors appreciably reduces the total harmonic distortion. The dependence of harmonic distortion on length of the lightly doped region is very weak.
Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET
(2005-09-05) PAIOLA, A. G.; NICOLETT, A. S.; MARTINO, J. A.
This work analyzes the influence of the gate oxide tunneling current on the extraction of the silicon film and front oxide thickness on deep submicrometer fully depleted SOI nMOSFET devices. Numerical bidimensional simulations to support the analysis and experimental measurements were done using 0.13 μm SOI CMOS technology.
Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMoSFETs
(2005-09-07) Milene Galeti; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
This paper presents an analysis of the gate oxide thickness and temperature influence on the carrier generation lifetime determination. The study is accomplished through two-dimensional numerical simulations in partially depleted SOI nMOSFETs and compared with experimental data of devices fabricated with a 0.13 μm SOI CMOS technology. The temperature varied from 20°C to 80°C and the gate oxide thickness between 1.5 nm and 3.5 nm. Beyond the generation lifetime, other electric parameters were also analyzed as the threshold voltage, the surface potential, the activation energy and the gate current. A reduction of surface potential was observed for an increase in the gate oxide thickness, specially in the steady state surface potential. In the present study, the decrease in gate oxide thickness caused a maximum of 2% variation in the activation energy. For the step bias used, the gate current is not enough large to control the body charging and makes it less sensitive to transient effects.
Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs
(2005-09-07) BELLODI, M.; MARTINO, J. A.
Experimental and simulations analyzes were done in Graded-Channel (GC) SOI nMOSFETs in order to study the drain leakage current behavior in these devices when operating from room temperature (300K) up to 573K. It was noticed that drain leakage current depends strongly on the ratio between the length of the lowly doped region and the mask channel length. All discussions presented are based on experimental and numerical bidimensional simulations results.
Comparison between bulk and floating body partially depleted SOI nMOSFETS for high frequency analog applications operating from 300 K down to 95 K
(2005-09-07) Marcelo Antonio Pavanello; MARTINO, J. A.; SIMOEN, E.; CLAEYS, C.
A comparison between deep-submicrometer bulk and floating-body partially depleted (PD) SOI nMOSFET operation for high frequency analog applications is performed from room temperature down to 95 K. The transistor intrinsic gain, cutoff frequency and bias current are used as figures of merit for this comparison. It is demonstrated that bulk transistors can have larger intrinsic gain at any temperature of operation due to their larger Early voltage. On the other hand, the cutoff frequency is improved in PD SOI without halo due to the larger carrier mobility and velocity saturation. Also PD SOI without halo reaches a frequency of 13 GHz at 95 K, whereas bulk and PD SOI with halo reach 11 GHz for the same load capacitance of 100 fF.

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