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Navegando Artigo de evento por Autor "CERDEIRA, A."

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    Artigo de evento
    Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures
    (2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.
    An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.
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    Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors
    (2010-09-05) CONTRERAS, E.; CERDEIRA, A.; ALVARADO, J.; Marcelo Antonio Pavanello
    The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.
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    Artigo de evento
    Channel length reduction influence on harmonic distortion of graded-channel gate-all-around devices
    (2006-09-01) Rodrigo Doria; Marcelo Antonio Pavanello; CERDEIRA, A.; RASKIN, J. P.; FLANDRE, D.
    This work compares the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices for analog operation as in an amplifier when the channel length is scaled. The study has been performed through two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar bias the performance of GC GAA transistors remains better than the uniformly doped GAA for any channel length. Although scaling the devices tends to degrade the harmonic distortion, significant results were obtained for the GC configuration measured as an improvement of more than 15 dB in total harmonic distortion-to-gain ratio operating in the same region with channel length of 1uμm and with lightly doped region length of 0.3 μm. © 2006 The Electrochemical Society.
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    Artigo de evento
    Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
    (2005-09-07) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.
    The performance evaluation of conventional and graded-channel SOI MOSFETs operating as tunable resistors is performed from room temperature down to 90 K. The on-resistance, total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the on-resistance reduces with the temperature lowering and is smaller in any GC SOI than in conventional SOI due to the effective channel length reduction. The total harmonic distortion is weakly temperature dependent and decreases in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion is strongly temperature influenced, increasing 15 dB at 90 K with respect to room temperature operation. Conventional and GC SOI have similar third order harmonic distortion in all studied temperatures.
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    Artigo de evento
    Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications
    (2005-05-20) Marcelo Antonio Pavanello; CERDEIRA, A.; ALEMAN, M. A.; Joao Antonio Martino; VANCAILLE, L.; FLANDRE, D.
    An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature down to 90 K. The total harmonic distortion as a function of the transconductance over drain current ratio has been adopted as figure of merit. It is shown that the total harmonic distortion increases as the input voltage rises and the temperature is lowered. The use of lateral channel engineering in graded-channel transistors appreciably reduces the total harmonic distortion. The dependence of harmonic distortion on length of the lightly doped region is very weak.
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    Artigo de evento
    On-resistance and harmonic distortion in graded-channel SOI FD MOSFET
    (2004-11-05) CERDEIRA, A.; ALEMAN, M. A.; Marcelo Antonio Pavanello; MARTINO, J. A.; VANCAILLIE, L.; FLANDRE, D.
    In this paper we analyze the advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The study of the two major figures of merit in such applications, i.e. on-resistance and non-linear harmonic distortion, is supported by measurements on conventional and Graded-Channel (GC) fully depleted (FD) SOI MOSFETs. The quasi linear I-V characteristics of GC transistors demonstrate a decrease of the on-resistance as the length of the low doped region into the channel is augmented and an improvement of the third order harmonic distortion (HD3), when compared with conventional transistors. A full comparison method between conventional and GC SOI MOSFETs is presented considering HD3 evolution with on-resistance tuning under low voltage of operation, demonstrating the significant advantages of the asymmetrical long channel transistors. © 2004 IEEE.