Navegando por Autor "CERDEIRA, A."

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3D simulation of Triple-Gate MOSFETs
(2010-05-19) CONDE, J.; CERDEIRA, A.; Marcelo Antonio Pavanello; KILCHYTSKA, V.; FLANDRE, D.
In this paper we present a new approach of analyzing 3D structure for Triple-Gate MOSFETs with three different mesh regions, one at the top and two in the sidewalls of the fin, which allows the consideration of different carrier mobility at each region due to the crystalline orientation and technological processing. A procedure for the extraction of the mobility parameters in each region is developed. Validation of the proposed structure was made for a FinFET arrays with fixed channel length and different fin widths, obtaining a very good coincidence between experimental and simulated characteristics. © 2010 IEEE.
3D simulation of triple-gate MOSFETs with different mobility regions
(2011-07-05) CONDE, J.; CERDEIRA, A.; Marcelo Antonio Pavanello; KILCHYTSKA, V.; FLANDRE, D.
In this paper we present a new approach for analyzing 3D structure triple-gate MOSFETs using three different regions, one at the top and two in the sidewalls of the fin, which allows for considering different carrier mobilities in each region due to crystalline orientation and technological processing. A procedure for the extraction of the mobility parameters in each region is developed. Robustness of the proposed structure is validated by experimental data obtained on FinFETs. A very good agreement is obtained between experimental and simulated characteristics. © 2011 Elsevier B.V. All rights reserved.
3D triple-gate simulation considering the crystallographic orientations
(2008-09-04) CONDE, J. E.; CERDEIRA, A.; Marcelo Antonio Pavanello
Current in FinFET's transistors flows along two different crystallographic orientations, since, typically the FIN top region orientation is <100>, while the sidewalls have <110> orientation. In this paper we present how to represent the mesh structure for these devices, in order to simulate in 3-D, considering different mobility values for each orientation. Results of 3-D simulation considering also the effect of the series resistance are shown and compared with experimental results. © The Electrochemical Society.
A series association model for double gate graded-channel SOI nMOSFET analog circuit simulation
(2008-09-04) FERREIRA, F. A. L.P.; CERDEIRA, A.; Marcelo Antonio Pavanello
In this work we present the development of an equivalent series association analytical model for double gate (DG) Silicon-on-Insulator (SOI) nMOSFET transistor with graded-channel (GC) that is valid from weak inversion to strong inversion. Through the use of DG analytical models available in the literature, considering an equivalent structure represented by two transistors with different doping levels in series association, with short-circuited gates, each one simulating a GC channel region, we have got a model of the DG GC SOI nMOSFET. Atlas numerical two-dimensional simulations and experimental results are used to validate the proposed model. Good agreement between simulated, modelled and experimental results is found. © The Electrochemical Society.
Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range
(2018-03-19) CERDEIRA, A.; AVILA-HERRERA, F.; ESTRADA, M.; DORIA, R. T.; Marcelo Antonio Pavanello
This paper presents the necessary adaptions on the proposed compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range. The model validation is performed by comparison against experimental results showing very good agreement, with continuous current and its derivatives in all regions of operation and temperatures.
Analysis of bulk and accumulation mobilities in n- and p-type triple gate junctionless nanowire transistors
(2017-07-28) RIBEIRO, T. A.; Marcelo Antonio Pavanello; CERDEIRA, A.
This paper studies the effective mobility in n- and p-type junctionless nanowire transistors (JNT) with variable fin width from quasi-planar to nanowire devices. JNTs electrical parameters were analyzed and the results show that smaller fin width have higher mobility while the mobility decreases for quasi-planar devices. Simulations were used to analyze the mobility showing that small fin devices reach higher mobility for smaller gate bias variation above the threshold voltage and a higher mobility in the middle of the channel due to the better electrostatic coupling compared to larger devices.
Analysis of charges densities in multiple-gates SOI nMOS junctionless
(2013-09-06) MARINIELLO, G.; CERDEIRA, A.; ESTRADA, M.; Rodrido Doria; TREVISOLI, R. D.; Michelly De Souza; Marcelo Antonio Pavanello
This paper aims to analyze the charges density in multiple gates junctionless devices with different dimensions The analysis of the charge densities was done at the center of the silicon film, at the sidewall and at the top interfaces between the silicon and the gate oxide, for devices with different fin width, height and gate oxide tickness. Based on this analisys, the occurrence of corner effects in Junctionless devices is investigated. © 2013 IEEE.
Analysis of harmonic distortion in graded-channel SOI MOSFETS at high temperatures
(2004-09-11) Marcelo Antonio Pavanello; CERDEIRA, A.; MARTINO, J. A.; ALEMAN, M. A.; FLANDRE, D.
An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.
Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures
(2022-07-04) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Marcelo Antonio Pavanello
© 2022 IEEE.This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K and 580 K. The study is conducted using experimental data, corroborated with 3D TCAD simulations. It is demonstrated that the GIDL current normalized by the total fin width is larger in nanosheet MOSFET than for the nanowire at high temperatures. Additionally, the nanosheet device presents a larger variation of the normalized GIDL current with the temperature than the nanowire one.
Analytical compact model for triple gate junctionless MOSFETs
(2015-10-13) HERRERA, F. A.; CERDEIRA, A.; PAZ, B. C.; ESTRADA, M.; Marcelo Antonio Pavanello
A new compact analytical model for triple gate junctionless transistors JLT is presented considering the capacitances when the fin height is reduced. For its calculation, the capacitance is separated into gate and silicon height capacitance. On the modeling side, threshold voltage, drain current model and short channel effects are modeled considering the influence of variable fin height. Based on our previous developed analytical model for 2D devices, which neglects the fin height effects, a 3D analytical compact model was developed including short channel effects. The 3D model presented is useful for modeling silicon triple gate junctionless transistors. The model validation is done by simulations varying the fin height and channel length.
Analytical model for potential in double-gate juntionless transistors
(2013-09-06) CERDEIRA, A.; ESTRADA, M.; TREVISOLI, R. D.; Rodrido Doria; Michelly De Souza; Marcelo Antonio Pavanello
An analytical model to calculate the potential at the surface and at the center of silicon layer for long-channel Junctionless transistors is derived and explained the basic details. The analytical model is compared with the numerical solution of the fundamental equations showing the validity of the assumptions considered. © 2013 IEEE.
Analytical modeling of double gate graded-channel SOI transistors for analog applications
(2009-05-29) FERREIRA, F. A. L. P.; CERDEIRA, A.; FLANDRE, D.; Marcelo Antonio Pavanello
In this work we present the development of an analytical model for double gate (DG) Silicon-on-Insulator (SOI) nMOSFET transistor with graded-channel (GC), valid from weak inversion to strong inversion. Atlas numerical two-dimensional simulations and experimental results are used to validate the proposed model. Good agreement between simulated, modeled and experimental results is demonstrated. ©The Electrochemical Society.
Application of double gate graded-channel SOI in MOSFET-C balanced structures
(2007-05-11) Rodrigo Doria; Marcelo Antonio Pavanello; CERDEIRA, A.; RASKIN J. P.; FLANDRE, D.
This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices when applied in 2-MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive. © The Electrochemical Society.
Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors
(2010-09-05) CONTRERAS, E.; CERDEIRA, A.; ALVARADO, J.; Marcelo Antonio Pavanello
The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.
Application of the symmetric doped double-gate model in circuit simulation containing double-gate graded-channel transistors
(2009-09-03) CONTRERAS, E.; CERDEIRA, A.; ALVARADO J.; Marcelo Antonio Pavanello
The development of models to simulate circuits containing new devices is an important task to allow for the introduction of these devices in practical applications. In this paper we show the advantages of using the Symmetric Doped Double-Gate Model recently developed and are already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. A current-mirror circuit using GC devices has been simulated and the results were validated comparing them with those obtained in MIXED-MODE and two-dimensional ATLAS simulation of the GC devices. © The Electrochemical Society.
Channel length reduction influence on harmonic distortion of graded-channel gate-all-around devices
(2006-09-01) Rodrigo Doria; Marcelo Antonio Pavanello; CERDEIRA, A.; RASKIN, J. P.; FLANDRE, D.
This work compares the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices for analog operation as in an amplifier when the channel length is scaled. The study has been performed through two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar bias the performance of GC GAA transistors remains better than the uniformly doped GAA for any channel length. Although scaling the devices tends to degrade the harmonic distortion, significant results were obtained for the GC configuration measured as an improvement of more than 15 dB in total harmonic distortion-to-gain ratio operating in the same region with channel length of 1uμm and with lightly doped region length of 0.3 μm. © 2006 The Electrochemical Society.
From double to triple gate: Modeling junctionless nanowire transistors
(2015-03-18) PAZ, B. C.; Marcelo Antonio Pavanello; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; FAYNOT, O.; AVILA-HERRERA, F.; CERDEIRA, A.
This paper presents a continuous, physically and charge-based new model for triple gate junctionless nanowire transistors (3G JNT). The presented model was evolved from a previous one designed for double gate junctionless transistors (2G JNT). The capacitance coupling and the internal potential changing from 2G to 3G JNTs are considered. The model validation is performed through both numerical simulation and experimental measurements for long and short channel devices.
Graded-channel SOI nMOSFET model valid for harmonic distortion evaluation
(2006-05-17) Michelly De Souza; Marcelo Antonio Pavanello; CERDEIRA, A.; FLANDRE, D.
In this paper an evaluation of the harmonic distortion of graded-channel SOI nMOSFETs is performed. The analysis is carried out by comparing an analytical continuous model and experimental results. The total harmonic distortion, as well as the third and second order terms are used as figures of merit in this comparison. It is shown that GC SOI devices present better gain and linearity behavior than conventional devices and that these advantages are well described by the proposed analytical model. The results show that the proposed set of equations is able to describe the linearity behavior of GC devices, indicating its potential to be used in analog circuit simulation and design. © 2006 IEEE.
Harmonic distortion analysis of SOI triple gate FinFETs applied to 2-MOS balanced structures
(2009-05-29) Rodrigo Doria; MARTINO, J. A.; CERDEIRA, A.; Marcelo Antonio Pavanello
This work presents an evaluation of the non-linearities exhibited in 2-MOS resistive structures composed by triple gate FinFETs with several fin widths down to 30 nm. The harmonic distortion has been analysed in terms of its third order component (HD3) as a function of the gate voltage, the input amplitude voltage and the fin width. The linearity has also been analysed with respect to the on-resistance, which constitutes a key parameter in such circuits. Along the harmonic distortion evaluation, the non-linearity causes are pointed out. At lower gate voltages, wider devices present smaller HD3 with respect to the narrower ones, while the contrary occurs at higher gate voltages. ©The Electrochemical Society.
High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs
(2023-01-05) Michelly De Souza; CERDEIRA, A.; ESTRADA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; Pavanello M. A.
AuthorIn this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.